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Explore the interconnection structures and bus architecture in computer systems, including memory, I/O, and CPU connections, data transfer types, and the function of data, address, and control lines.
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William Stallings Computer Organization and Architecture Chapter 3 Top Level View of Computer Function and Interconnection Lecture 6 19/10/2015------SE 2/11/2015 30/10/2015----CS
Interconnection Structures • A computer consists of a set of components or modules of three basic types(processor, memory, I/O)that communicate with each other. • The collection of paths connecting the various modules is called the interconnection structure.
Memory Connection • Receives and sends data • Receives addresses (of locations) • Receives control signals • Read • Write
Input/Output Connection(1) • Similar to memory from computer’s viewpoint • Output • Receive data from computer • Send data to peripheral • Input • Receive data from peripheral • Send data to computer
Input/Output Connection(2) • Receive control signals from computer • Send control signals to peripherals • Receive addresses from computer • e.g. port number to identify peripheral • Send interrupt signals (control)
CPU Connection • Reads instruction and data • Writes out data (after processing) • Sends control signals to other units • Receives (& acts on) interrupts
The preceding list defines the data to be exchanged. The interconnection structure must support the following types of transfer. • Memory to processor: the processor reads an instruction or unit of data from memory • Processor to memory: the processor writes a unit of data to memory • I/O to processor: the processor reads data from an I/O device via an I/O module. • Processor to I/O: the processor sends data to the I/O device. • I/O to or from memory: an I/O module is allowed to exchange data directly with memory without going through processor, using direct memory access.
Bus Interconnection • A bus is a communication pathway connecting two or more devices. • It is a shared transmission medium. • Typically, a bus consist of multiple communication pathways or lines. • Each line is capable of transmitting signals representing binary 1 and binary 0. • Over time, a sequence of binary digits can be transmitted across a single line. • Taken together, several lines of a bus can be used to transmit binary data simultaneously (in parallel) • For example: an 8 bit unit of data can be transmitted over eight bus lines.
System Bus • Computer systems contain a number of different buses that provide pathways between components at various levels of the computer system hierarchy. • A bus that connects major computer components (processor, memory, I/O) is called a system bus.
Bus Structure • A system bus consists of from about fifty to hundreds of separate lines. • Each line is assigned a particular meaning or function. • The lines can be classified into three functional groups: data, address and control lines.
Data Bus • The data lines provide a path for moving data among system modules. • These lines collectively are called data bus. • The data bus may consists of 32, 64, 128 or more separate lines. • The number of lines are the width of the data bus. • The number of lines determine how many bits can be transferred at a time. • Width is a key determinant of performance
Address bus • Identify the source or destination of data • e.g. CPU needs to read an instruction (data) from a given location in memory • Bus width determines maximum memory capacity of system • Address lines are also used to address I/O ports. The higher order bits are used to select a particular module on the bus, and the lower order bit select a memory location or I/O port within the module.
For example: on an 8 bit address bus, address 01111111 and below might reference locations in a memory module (module 0) with 128 words of memory • And address 10000000 and above refer to devices attached to an I/O module (module 1)
Control Bus • The control lines are used to control the access to and the use of data and address lines. • Since the data and address lines are shared by all components, there must be a means of controlling their use. • Control signal transmit both command and timing information among system modules. • Timing signal indicate the validity of data and address information. • Command signal specify operation to be performed.
Typical control lines include: • Memory write: causes data on the bus to be written into the addressed location. • Memory read: causes data from the addressed location to be placed on the bus. • I/O write: causes data on the bus to be output to the addressed I/O port. • I/O read: causes data from the addressed I/O port to be placed on the bus. • Transfer ACK: indicates that data have been accepted from or placed on the bus. • Bus Request: indicates that a module needs to gain control of the bus
Bus grant: indicates that a requesting module has been granted control of the bus. • Interrupt request: indicates that an interrupt is pending. • Interrupt ACK: acknowledges that the pending interrupt has been recognized • Clock: is used to synchronize operations • Reset: initializes all modules.
Single Bus Problems • Lots of devices on one bus leads to: • Propagation delays • Long data paths mean that co-ordination of bus use can adversely affect performance • If aggregate data transfer demand approaches the bus capacity • Most systems use multiple buses to overcome these problems
Elements of Bus Design: 1 Bus Types • Dedicated • Separate data & address lines • Multiplexed • Shared lines • Address valid or data valid control line • Advantage - fewer lines • Disadvantages • More complex circuitry • Performance is reduced
2 Method of Arbitration • More than one module may need control of the bus. • But only one module can successfully transmit over the bus. • Some method of arbitration is needed. • Arbitration may be centralised or distributed
Centralised or Distributed Arbitration • Centralised • Single hardware device controls the bus access; which is called • Bus Controller • Arbiter • The device may be part of CPU or separate • Distributed • Each module may claim the bus • Control logic on all modules • In a single exchange of data, one device becomes master and sends data, other device becomes slave and receives data.
3 Timing • Timing refers to the way in which events are coordinated on the bus. • Buses use either synchronous timing or asynchronous timing. • Synchronous • Events determined by clock signals • Control Bus includes clock line • A single 1-0 is a bus cycle • All devices on the bus can read clock line • All events start at the beginning of a clock cycle. • Usually sync on leading edge • Usually a single cycle for an event
Synchronous timing is simpler to implement and test. However, it is less flexible than asynchronous timing. Because all devices on a synchronous bus are tied to a fixed clock rate, the system cannot take advantage of advances in device performance. With asynchronous timing, a mixture of slow and fast devices can share a bus.
