Bas ic data about TTU

3. Basic data about TTU • Founded as engineering college in 1918, TTU acquired university status in 1936. • TTU has about 9000 students and 1209 employees, offering engineering and economics diploma studies, bachelor, master and doctorate degree programmes. • Academic part of the university is organised into • 8 faculties, • 30 departments and 108 chairs, • 7centres and • 9 affiliated institutions.

4. Number of graduates, Febr. 2002

5. Faculties at TU Tallinn with Students

6. Admission of Students

7. R&D funding in 2000 Total 106,3 mill. EEK (6,8 mill. €)

8. Our Partners TTU cooperates with about 20-30 universities KTH LIU TTU Jonköping USA: Michigan U Dresden East- and Middle-Europe Kharkov Ilmenau Costa Rica Darmstadt Stuttgart Grenoble Indonesia Torino

9. Test Generation and Fault Simulation for Digital Systems Kharkov National University of Radioelectronics Kharkov, Ukraine April 5-7, 2004 Raimund Ubar www.pld.ttu.ee/~raiub Tallinn Technical University D&T Laboratory Estonia

10. Motivation of the Course • The increasing complexity of VLSI circuits has made test generation one of the most complicated and time-consuming problems in digital design • The more complex are getting systems, the more important will be the problems of test and design for testability because of the very high cost of testing electronic products • Engineers involved in SoC design and technology should be • made better aware of the importance of test, • very close relationships between design and test, and • trained in test technology to enable them to design and produce high quality, defect-free and fault-tolerant products

11. Goals of the Course • The main goal of the course is to give the basic knowledge to answer the question: How toimprove the testing quality at increasing complexities of today's systems? • This knowledges includes • understanding of how the physical defects can influence on the behavior of systems, and how the fault modelling can be carried out • learning the basic techniques of fault simulation, test generation and fault diagnosis • understanding the meaning of testability, and how the testability of a system can be measured and improved • learning the basic methods of making systems self-testable • The goal is also to give some hands-on experience of solving test related problems

12. Objective of the Course VLSI Design Flow Verification Simulation. Timing analysis, formal verification Specification Hardware description languages (VHDL) Implementation Full custom, standard cell, gate arrays Testing Fault modeling Test generation Fault simulation Manufacturing CMOS

13. Test Environment Test experiment Test result System (BIST) Fault simulation Fault diagnosis System model Fault dictionary Test Go/No go Located defect Test generation Test tools

14. Topics Map Theory Models Defect Level Boolean Differential Analysis Fault Modelling High Level Tools Hierarchical approaches Decision Diagrams Fault Simulation Test Generation High Level System Modelling Logic Level BDD

15. Abstract • How toimprove the testing quality at increasing complexities of today's systems? • Two main trends: defect-oriented test and high-level modelling • Both are caused by the increasing complexities of systems based on deep-submicron technologies • The complexity problems in testing digital systems are handled by raising the abstraction levels from gate to register-transfer level (RTL) instruction set architecture (ISA)or behavioral levels • To handle defects in circuits implemented in deep-submicron technologies, new fault models and defect-oriented test methods should be used • Trends to high-level modelling and defect-orientation are opposite • As a promising compromise and solution is:to combine hierarchical approach with defect orientation • Decision Diagrams serve as a good tool forhierarchical modelling of defects in digital systems

16. Outline • Introduction to Digital Test (5) • How to improve test quality at increasing complexity of systems (9) • High-level modelling and defect-orientation (25) • BDDs and logic level testing • Hierarchical test generation (42) • General concepts • Test generation for RT Level systems • Test generation for Microprocessors • Hierarchical fault simulation (62) • Overview of tools developed at D&T Lab (70)

17. Introduction: the Problem is Money? How to succeed? Try too hard! How to fail? Try too hard! (From American Wisdom) Cost of quality Cost Cost of testing 100% Test coverage function Cost of the fault Time Conclusion: “The problem of testing can only be contained not solved” T.Williams Quality Optimum test / quality 0% 100%

18. Introduction All life is an experiment. The more experiments you make, the better (American Wisdom) Paradox 1: Digital world is finite, analog world is infinite. However, the complexity problem was introduced by Digital World Paradox 2: If I can show that the system works, then it should be not faulty. But, what does it mean: it works? 32-bit accumulator has 264 functions which all should work. So, you should test all the 264 functions! Stimuli Response Y System X Digital case (“continuous”) Y Analog case (samples) X

19. Introduction: How Much to Test? Time can be your best friend or your worst enemy (Ray Charles) Paradox: 264 input patterns (!) for 32-bit accumulator will be not enough. A short will change the circuit into sequential one, and you will need because of that 265 input patterns Paradox: Mathematicians counted that Intel 8080 needed for exhaustive testing 37 (!) years Manufacturer did it by 10 seconds Majority of functions will never activated during the lifetime of the system Y = F(x1, x2, x3) Bridging fault State q 0 y x1 & 1 & x2 * x3 1 Y = F(x1, x2, x3,q)

20. Introduction: Hierarchy The best place to start is with a good title. Then build a song around it. (Wisdom of country music) Paradox: To generate a test for a block in a system, the computer needed 2 days and 2 nights An engineer did it by hand with 15 minutes So, why computers? Sea of gates & Sequence of 216 bits 16 bit counter 1 System

21. Introduction: Quality Policy Defect level (DL) Pa Yield (Y) P,n Quality policy Design for testability P - probability of a defect n - number of defects Pa - probability of accepting a bad product Testing - probability of producing a good product

22. Introduction: Defect Level DL Y Y(%) 1 90 8 5 1 T(%) 45 25 5 50 0 100 10 81 45 9 T(%) DL   T  10 50 90 Paradox: Testability DL 

23. Introduction: Design for Testability • Theorem: You can test an arbitrary digital system by only 3 test patterns • if you design it approprietly Amusing testability: Proof: 011 011 001 & & 001 & 101 101 ? 011 001 & 011 1 101 & 010 001 101 Solution: System  FSM  Scan-Path  CC  NAND

24. Outline • Introduction to Digital Test • How to improve test quality at increasing complexity of systems • High-level modelling and defect-orientation • BDDs and logic level testing • Hierarchical test generation • General concepts • Test generation for RT Level systems • Test generation for Microprocessors • Hierarchical fault simulation • Overview of tools developed at D&T Lab

25. Complexity vs. Quality Problems: • Traditional low-level test generation and fault simulation methods and tools for digital systems have lost their importancebecause of the complexityreasons • Traditional Stuck-at Fault (SAF) model does not quarantee the qualityfor deep-submicron technologies New solutions: • The complexity can bereduced by raising the abstraction levels from gate to RTL, ISA, and behavioral levels • But this moves us even more away from the real life of defects (!) • To handle adequately defects in deep-submicron technologies, new fault models and defect-oriented test generation methods should be used • But, this is increasing even more the complexity (!) • To get out from the deadlock, these two opposite trends should be combined into hierarchical approaches

26. Fault and defect modeling Defects, errors and faults • An instance of an incorrect operation of the system being tested is referred to as an error • The causes of the observed errors may be design errors or physical faults -defects • Physical faults do not allow a direct mathematical treatment of testing and diagnosis • The solution is to deal with fault models System Defect Component Fault Error

27. Fault and defect modeling x1 a x21 & x2 Fault models are: explicit and implicit • explicit faults may be enumerated • implicit faults are given by some characterizing properties Fault models are: structural and functional: • structural faults are related to structural models, they modify interconnections between components • functional faults are related to functional models, they modify functions of components y 1 x22 & x3 b Structural faults: - line a is broken - short between x2and x3 Functional fault: Instead of

28. Transistor Level Faults Stuck-at-1 Broken (change of the function) Bridging Stuck-open NewState Stuck-on (change of the function) Short (change of the function) Stuck-off (change of the function) Stuck-at-0 SAF-model is not able to cover all the transistor level defects How to model transistor defects ?

29. Mapping Transistor Faults to Logic Level A transistor fault causes a change in a logic function not representable by SAF model Function: y Faulty function: x1 x4 Short 0 – defect d is missing 1 – defect d is present d= Defect variable: x2 Generic function with defect: x5 x3 Mapping the physical defect onto the logic level by solving the equation:

30. Boolean Derivatives Traditional algebra:speed Boolean algebra:change y = F(x) y 0,1, F(X) 0,1 y F(X)will change ifxi changes F(X)will not change ifxi changes x xi xk

31. Boolean derivatives Boolean function: Y = F(x) = F(x1, x2, … , xn) Boolean partial derivative:

32. Mapping Transistor Faults to Logic Level Function: Faulty function: Generic function with defect: y x1 x4 Short Test calculation by Boolean derivative: x2 x5 x3

33. Why Boolean Derivatives? Given: Distinguishing function: BD-based approach: Using the properties of BDs, the procedure of solving the equation becomes easier

34. Functional Fault vs. Stuck-at Fault Full 100% Stuck-at-Fault-Test is not able to detect the short:  Functional fault The full SAF test is not covering any of the patterns able to detect the given transistor defect

35. Defect coverage for 100% Stuck-at Test Results: • the difference between stuck-at fault and physical defect coverages reduces when the complexity of the circuit increases (C2 is more complex than C1) • the difference between stuck-at fault and physical defect coverages is higher when the defect probabilities are taken into account compared to the traditional method where all faults are assumed to have the same probability

36. Generalization: Functional Fault Model Fault-free Faulty Constraints calculation: d = 1, if the defect is present Component with defect: Constraints: Component F(x1,x2,…,xn) y Wd Defect Fault model: d:(dy,Wd), {dj}: (dy,{Wkd,j}) Logical constraints

37. Functional Fault Model Examples Constraints: Component with defect: Component F(x1,x2,…,xn) y Wd Constraints examples: Defect Logical constraints FF model: (dy,Wd), (dy,{Wkd})

38. Functional Fault Model for Stuck-ON NOR gate Stuck-on VDD x1 RN x2 Y x1 x2 RP VSS Condition of the fault potential detecting: Conducting path for “10”

39. Functional Fault Model for Stuck-Open NOR gate Test sequence is needed: 00,10 Stuck-off (open) tx1 x2 y 1 0 0 1 2 1 0 1 VDD x1 x2 Y x1 x2 VSS No conducting path from VDD to VSS for “10”

40. Functional Fault Model x*k xk d Example: Bridging faultbetween leadsxkandxl The conditionmeans that in order to detect the short between leadsxkand xl on the leadxk we have to assign toxkthe value 1 and toxlthe value 0. xl xk*= f(xk,xl,d) Wired-AND model

41. Functional Fault Model Bridging fault causes a feedback loop: Example: A short between leads xkand xlchanges the combinational circuit into sequential one x1 y & x2 & x3 Equivalent faulty circuit: x1 y & & x2 x3 tx1 x2 x3 y 1 0 1 0 2 1 1 1 1 Sequential constraints: &

42. Mapping High level k WFk Component Low level WSk Bridging fault Environment Mapping First Step to Quality How to improve the test quality at the increasing complexity of systems? First step to solution: Functional fault model was introduced as a means for mapping physical defects from the transistor or layout level to the logic level System

43. Outline • Introduction to Digital Test • How to improve test quality at increasing complexity of systems • High-level modelling and defect-orientation • BDDs and logic level testing • Hierarchical test generation • General concepts • Test generation for RT Level systems • Test generation for Microprocessors • Hierarchical fault simulation • Overview of tools developed at D&T Lab

44. Register Level Fault Models RTL statement: K: (If T,C) RD F(RS1, RS2, … RSm),  N Components (variables) of the statement: RT level faults: K  K’ - label faults T  T’ - timing faults C  C’ - logical condition faults RD RD - register decoding faults RS RS - data storage faults F  F’ - operation decoding faults  - data transfer faults  N - control faults (F)  (F)’ - data manipulation faults K - label T - timing condition C - logical condition RD - destination register RS - source register F - operation (microoperation)  - data transfer  N - jump to the next statement

45. Fault Models for High-Level Components Decoder: - instead of correct line, incorrect is activated - in addition to correct line, additional line is activated - no lines are activated Multiplexer (n inputs log2 n control lines): - stuck-at - 0 (1) on inputs - another input (instead of, additional) - value, followed by its complement - value, followed by its complement on a line whose address differs in 1 bit Memory fault models: - one or more cells stuck-at - 0 (1) - two or more cells coupled

46. Fault models and Tests Functional fault model Dedicated functional fault model for multiplexer: • stuck-at-0 (1) on inputs, • another input (instead of, additional) • value, followed by its complement • value, followed by its complement on a line whose address differs in one bit Test description

47. Faults and Test Generation Hierarchy Functional Structural Higher Level Module approach approach ki k Component Lower level WFki S Test F W k WFk WSki System Network Bridging fault F W of modules k Environment S Test W F k ki Interpretation of WFk: - asa test on the lower level - asa functional fault on the higher level Module Network F W ki of gates d W Test F ki ki Circuit e Gat

48. Hierarchical Defect-Oriented Test Analysis BDDs DDs

49. Outline • Introduction to Digital Test • How to improve test quality at increasing complexity of systems • High-level modelling and defect-orientation • BDDs and logic level testing • Hierarchical test generation • General concepts • Test generation for RT Level systems • Test generation for Microprocessors • Hierarchical fault simulation • Overview of tools developed at D&T Lab