Control Unit Operation

1. Group 1 Michael Bouizza Rolando Abreu Carlos De Cossio Ricardo Urena Michael Hernandez Robert Romano Sun Li Yang Control Unit Operation

2. Micro-Operations • A computer executes a program • Fetch/execute cycle • Each cycle has a number of steps • Called micro-operations • Atomic operation of CPU

3. Constituent Elements of Program Execution

4. Fetch - 4 Registers • Memory Address Register (MAR) • Memory Buffer Register (MBR) • Program Counter (PC) • Instruction Register (IR)

5. Fetch Sequence • Address of next instruction is in PC • Address (MAR) is placed on address bus • Control unit issues READ command • Result appears on data bus • Data from data bus copied into MBR • PC incremented by 1 • Data (instruction) moved from MBR to IR • MBR is now free for further data fetches

6. Fetch Sequence (symbolic) • t1: MAR <- (PC) • t2: MBR <- (memory) • PC <- (PC) +1 • t3: IR <- (MBR) • (tx = time unit/clock cycle) or • t1: MAR <- (PC) • t2: MBR <- (memory) • t3: PC <- (PC) +1 • IR <- (MBR)

7. Rules for Clock Cycle Grouping

8. Indirect Cycle

9. Interrupt Cycle

10. Execute Cycle (ADD) ADD R1, X

11. Execute Cycle (ISZ) ISZ X - increment and skip if zero

12. Execute Cycle (BSA) BSA X - Branch and Save Address Address of instruction following BSA is saved in X Execution continues from X+1

13. Instruction Cycle • Each phase decomposed into sequence of elementary micro-operations • Such as fetch, indirect, and interrupt cycles. • Execute cycle • One sequence of micro-operations for each opcode Assume new 2-bit register • Instruction cycle code (ICC) designates which part of cycle processor is in • 00: Fetch • 01: Indirect • 10: Execute • 11: Interrupt

14. Data Flow - Fetch Cycle

15. Data Flow – Indirect Cycle

16. Data Flow – Interrupt Cycle

17. Execute Cycle • Can take many forms, depending on the instruction located in the IR. • May Involve transferring data among registers, read/write from memory or I/O, and • This cycle may involve transferring data among registers, read or write from memory or I/O.

18. Functional Requirements • Define basic elements of processor • Describe micro-operations processor performs • Determine functions control unit must perform

19. CPU with the System Bus

20. Basic Elements of a Processor • ALU • Registers • Internal data paths • External data paths • Control Unit

21. Transfer data between registers Transfer data from register to external Transfer data from external to register Perform arithmetic or logical ops Types of Micro-operation

22. Functions of Control Unit • Sequencing • Causing the CPU to step through a series of micro-operations • Execution • Causing the performance of each micro-op

23. Control Signals

24. Control Signals Output Electronic Signals that execute instructions • In CPU • Causes Data Transfer • Executes Instructions • In Control Bus • Sends instructions out to I/O devices Ex: Modem, Soundcard & Video card • Sends signals to Memory

25. Modern I/O Controllers • Serial ATA Raid Controller on PCI Express

26. Control Signal Sequence – Fetch • MAR to PC • Opens Communication Between PC and MAR • MBR to Memory Steps Listed: • Opens Communication Between MAR and Address Bus • Memory gets Read Control Signal • Communication open Between Data Bus and MBR

27. Data Paths and Control Signals

28. Internal Organization • Single internal bus • Gates used in order to move through the buss • Control Signals will send out electronics signals to guide the transfer of information from the external systems bus • Temporary storage in registers are used for the proper functionality of ALU

29. CPU with Internal Bus

30. Intel 8085 CPU Block Diagram

31. Intel 8085 Pin Configuration

32. Intel 8085 OUT InstructionTimingDiagram

33. Hardwired Implementation • The control unit inputs signals are a combination of: • Opcode Bits. • Other signals such as interrupts, or condition codes. • Timing info (T1 to Tn). These signals are essential for timing for proper sequencing through instruction cycles.

34. Control Unit with Decoded Inputs

35. Hardwired Implementation • Instruction register the part of the CPU’s control unit that stores the instruction currently being executed or decoded. • Op-code causes different control signals for each different instruction • Unique logic for each op-code • Decoder takes encoded input and produces single output • n binary inputs and 2n outputs

36. Hardwired Implementation • Clock • Repetitive sequence of pulses • Useful for measuring duration of micro-ops • Must be long enough to allow signal propagation • Different control signals at different times within instruction cycle • Need a counter with different control signals for t1, t2 etc.

37. Problems With Hard Wired Designs • Complex sequencing & micro-operation logic • Difficult to design and test • Inflexible design • Difficult to add new instructions

38. Questions • What are a micro operations ? • Why should you not read and write from the same register at the same time ? • what are the basic elements of a processor ? • what happens when interupts are enabled ? • Name 3 sub-cycles for the instruction cycles

39. More Questions • How many types of micro-operation? • What are the inputs of the control signals? • List modern I/O Devices • What sends an electronic signals that organizes various processor unit to execute an instruction ? • What are advantages of hardware implementation ?

40. References • http://cnx.org/content/m29366/latest/ • http://en.wikipedia.org/wiki/Arithmetic_logic_unit • http://www.cs.toronto.edu/~hehner/csc258/comp.html\ • http://www.seas.upenn.edu/~palsetia/cit595s08/Lectures08/control1.pdf • http://www.hc11.demon.nl/thrsim11/68hc11/