Control Unit Operation Week 13

1. Control Unit Operation Week 13 Computer Architecture Computer Architecture

2. Review Keywords & Concepts • English words & ideas you must know: • Complementer • Shifter • PSW • Supervisor (kernel) mode • Interrupt processing • Pipelining Computer Architecture

3. What we will learn today • Collect Homework • Review last class • Control Unit Operations • Micro-Operations • Fetch cycle • Indirect cycle • Interrupt cycle • Execute cycle • Instruction cycle • Control of the Processor • Functional requirements • Control signals • Internal processor organization • QUIZ Computer Architecture

4. Processor Organization • Requirements • Fetch Instruction (from memory) • Interpret Instruction (decode instruction) • Fetch Data (from memory or i/o) • Process Data (perform operation) • Write Data (to memory or i/o) Computer Architecture

5. Internal Structure of CPU • ALU (Arithmetic Logic Unit) • Status flags • Shifter (logical, arithmetic & circular) • Complementer (flip / invert all bits) • Arithmetic & Boolean logic (+, *, /, OR, AND, NOT…) • Internal CPU bus • Registers • Control Unit Computer Architecture

6. PSW (Program Status Word) • Sign – sign bit of last arithmetic operation • Zero – set when result is zero • Carry – set if carry into or borrow (out of) high-order bit • Equal – set if logical compare result is equality • Overflow – set to indicate arithmetic overflow • Interrupt bit – used to enable or disable interrupts • Supervisor – bit indicating supervisor (kernel) mode or user mode Computer Architecture

7. Instruction Pipelining • Instruction processing in small steps • Fetch Instruction (FI) • Decode Instruction (DI) • Calculate Operands (CO) • Fetch Operands (FO) • Execute Instruction (EI) • Write Operand (WO) Computer Architecture

8. Micro-Operations • Program Execution • Instruction cycle • Fetch • Micro-operations • Indirect • Micro-operations • Execute • Micro-operations • Interrupt • Micro-operations Computer Architecture

9. Clock Cycles • Clock – on motherboard (external clock) • 3.0 GHZ  3,000,000,000 cycles / second • Clock – for RAM • 533 MHZ  533,000,000 cycles / second • Clock – in CPU • 12 cycles / external clock cycle (for example) • Timing considerations • Synchronizations • Gate delays Computer Architecture

10. Fetch Cycle • Fetch • T1: move the contents of PC to MAR • T2: activate BUS to fetch memory location (MAR) into MBR increment PC by instruction size • T3: move contents of MBR to IR Computer Architecture

11. Indirect Cycle • Indirect (only used if indirect bit is set) • T1: move the address in the IR to the MAR • T2: activate BUS to fetch memory location (MAR) into MBR • T3: update the address in the IR with MBR Computer Architecture

12. Execute Cycle • Execute (many possible sub-cycles) • Example: add R1,X • T1: move the address in the IR to the MAR • T2: activate BUS to fetch memory location (MAR) into MBR • T3: add contents of MBR to contents of R1 Computer Architecture

13. Interrupt Cycle • Interrupt • T1: move contents of PC to MBR • T2: move ‘save-address’ to MAR move ‘interrupt-address’ to PC • T3: activate BUS to store memory location (MAR) into MBR NOTE: maybe also have to store (i.e. save) the contents of all the registers – unless the CPU has an EXTRA set of registers for supervisor (kernel) mode)! User program MAY have intermediate data in the registers. Computer Architecture

14. Instruction Cycle • ICC – Instruction Cycle Code • 00: fetch • 01: indirect • 10: execute • 11: interrupt Computer Architecture

15. Processor (CPU) Control Signals • Control Unit (in CPU chip) • Inputs • Clock • Instruction Register • Flags • Control signals from (internal) control bus • Outputs • Control signals within the processor • Control signals to control (external) BUS Computer Architecture

16. Internal CPU BUS • IR (in the control unit) • PC • MAR (connects to external BUS) • MBR (connects to external BUS) • AC (accumulator – registers) • ALU • X register • Y register Computer Architecture

17. What you know now • Control Unit Operations • Micro-Operations • Fetch cycle • Indirect cycle • Interrupt cycle • Execute cycle • Instruction cycle • Control of the Processor • Functional requirements • Control signals • Internal processor organization Computer Architecture

18. Reading • http://en.wikipedia.org/wiki/Micro-operation • http://en.wikipedia.org/wiki/Microcode • http://en.wikipedia.org/wiki/Instruction_cycle Next Lecture (Two TOPICS!) • Reduced Instruction Set Computers (overview) • Parallel Processing (overview) Computer Architecture

19. HomeworkWeek 13 Check web page for homework assignment! Computer Architecture