Chip Timing Goals

Chip Timing Goals Min chip frequency : 200mHz Max transition rates : 400ps Implement clock tree

Overall timing flow

Global_timing.tcl

Chip Timing

Slew Limits Drove CTS towards clk slews of 250ps Drove synthesis towards data slews to 350ps Final design has 10 nets that fail 400ps data slew With more time would do more buffering on these nets

Clock Skew

Metal fill spf issue Towards the end of the design we decided to put in metal fill for DFM reasons which caused ICC to output 2 spf files (or1200_top.spf.max and or1200_top.spf.min) instead of the initial single spf file When we ran primetime with either of these spf.max or spf.min parasitics files, timing broke We later realized that this was due to metal fill being added before extraction and thus the spf.max and spf.min files were likely manhatten distance parasitics. Thus we made another run in which we reextracted after metal fill and this solved our issue

Final Results Max slack : 87ps Min slack : 305ps Slew : all 400ps or less aside from 10 nets, 8 of which are at 480ps and 2 of which at 536ps Clock slew driven to 250ps

Takeaways for the future Implement CTS earlier Initial slew constraints can be looser but final slew constraints can be tighter More time to investigate extraction process and .spf file format More robust slew violation catching script

Chip Timing Goals

Chip Timing Goals

Presentation Transcript

ChIP on ChIP

ChIP-chip and ChIP-seq

Timing

Timing

Efficient Timing Channel Protection for On-Chip Networks

Clocking and Timing in Fault-Tolerant Systems-on-Chip

Timing

Timing

Timing

A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning

Timing

ChIP-chip Data

CHIP

Timing Analysis and Timing Predictability

chIP-chip For Transcriptome Research

Timing

Timing

Timing

PRECISION MICROFLUIDIC OSCILLATORS FOR ON-CHIP TIMING AND CONTROL

Timing