A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning

1. A Timing-Driven Soft-MacroResynthesis Method in Interaction with ChipFloorplanning Hsiao-Pin Su12 Allen C.-H. Wu1 Youn-Long Lin1 1Department of Computer Science Tsing Hua University Hsinchu, Taiwan, R.O.C 2Taiwan Semiconductor Manufacturing Co., Ltd. {Email: robin@nthucad.cs.nthu.edu.tw}

2. Outline • Introduction • Motivation • The Proposed Method • Experiments • Conclusions

3. Yes A Typical HDL-based Design Flow RC-Extraction Delay Calculation RC-Extraction Delay Calculation HDL Description HDL Description Timing Analysis Timing Analysis HDL Synthesis HDL Synthesis No No Floorplanning Floorplanning OK? OK? Yes P & R P & R Chip Layout Chip Layout

4. Motivation • Develop a complete chip design method which incorporates a soft-macro placement and resynthesis method in interaction with chip floorplanning for area and timing improvement.

5. HM1 HM2 SM1 SM2 SM3 SM4 Motivation (cont’) Top HM1 HM2 SM2 SM3 SM1 SM4

6. The critical path delay Slack > 0 SM2 HM1 SM1 SM3 SM3 SM3 SM3 SM3 HM2 SM4 ( b ) Saved area Resynthesize SM3 by relaxing its timing constraints. Motivation (cont’) SM2 HM1 SM1 SM3 HM2 SM4 ( a )

7. Timing violation HM1 SM1 SM2 SM2 SM2 SM2 SM3 HM2 SM4 ( d ) Resynthesize SM2 by tightening its timing constraints. Motivation(cont’) SM2 HM1 SM1 SM3 HM2 SM4 ( c )

8. Considerations • How to decide HDL design hierarchy? • How to guide soft-macro placement by utilizing hierarchy information? • How to integrate design tasks and point tools at different design level to form a complete chip design methodology? • How to exploit the interaction between different design tasks?

9. The Proposed Method HDL Description P&R Routed database RTL netlist RC Extraction & Delay Calculation HDL Synthesis Timingconstraint SDF file Soft-Macro Formation Soft-Macro Formation Post-layout Timing Analysis Soft-Macro group Block Placement Timing Ok & no more area improvement Hard macro location Yes Yes No Soft-Macro Placement Soft-Macro Placement Module Resynthesis Module Resynthesis Chip Layout Soft-Macro location

10. The Proposed Method HDL Description P&R Routed database RTL netlist RC Extraction & Delay Calculation HDL Synthesis HDL Synthesis Timingconstraint SDF file Soft-Macro Formation Post-layout Timing Analysis Soft-Macro group Block Placement Timing Ok & no more area improvement Hard macro location Yes Yes No Soft-Macro Placement Module Resynthesis Chip Layout Soft-Macro location

11. The Proposed Method HDL Description P&R Routed database RTL netlist RC Extraction & Delay Calculation HDL Synthesis Timingconstraint SDF file Soft-Macro Formation Soft-Macro Formation Post-layout Timing Analysis Soft-Macro group Block Placement Timing Ok & no more area improvement Hard macro location Yes Yes No Soft-Macro Placement Module Resynthesis Chip Layout Soft-Macro location

12. Top HM1 HM2 SM2 SM3 SM1 SM4 Hierarchy-tree Construction • The main objective is to preserve the design hierarchy information from HDL design description during soft macro formation.

13. Soft-Macro Formation • Clock-based clustering • Group the macros connected to the same clock source into the same cluster. • Decomposition of large soft-macros. • A large macro is too rigid for macro Placement. • Clustering of small soft-macros. • Many small macros increase the computational complexity.

14. HM1 HM2 SM4 Clock-based Clustering • Partition circuit based on the clock connection. • Localize the distribution of clock signal. • If clock signal is distributed to many modules then it may have difficulty to balance the clock skew or cause area penalty when balance the clock skew on top module.

15. Large-Macro Decomposition • Split cluster if cluster size is larger than the size threshold by using FM partitioning method. • Big size threshold:

16. Small-Macros Clustering • Merge clusters if cluster size is smaller than the size threshold. • Small size threshold:

17. Clustering Cost Function • Cost Function: • Connectivity Consideration: • Criticality Consideration:

18. The Proposed Method HDL Description P&R Routed database RTL netlist RC Extraction & Delay Calculation HDL Synthesis Timingconstraint SDF file Soft-Macro Formation Soft-Macro Formation Post-layout Timing Analysis Soft-Macro group Block Placement Timing Ok & no more area improvement Hard macro location Yes Yes No Soft-Macro Placement Module Resynthesis Chip Layout Soft-Macro location

19. The Proposed Method HDL Description P&R Routed database RTL netlist RC Extraction & Delay Calculation HDL Synthesis Timingconstraint SDF file Soft-Macro Formation Soft-Macro Formation Post-layout Timing Analysis Soft-Macro group Block Placement Timing Ok & no more area improvement Hard macro location Yes Yes No Soft-Macro Placement Module Resynthesis Chip Layout Soft-Macro location

20. HM HM Block Placement IO IO IO IO

21. The Proposed Method HDL Description P&R Routed database RTL netlist RC Extraction & Delay Calculation HDL Synthesis Timingconstraint SDF file Soft-Macro Formation Soft-Macro Formation Post-layout Timing Analysis Soft-Macro group Block Placement Timing Ok & no more area improvement Hard macro location Yes Yes No Soft-Macro Placement Module Resynthesis Chip Layout Soft-Macro location

22. The Proposed Method HDL Description P&R Routed database RTL netlist RC Extraction & Delay Calculation HDL Synthesis Timingconstraint SDF file Soft-Macro Formation Soft-Macro Formation Post-layout Timing Analysis Soft-Macro group Block Placement Timing Ok & no more area improvement Hard macro location Yes Yes No Soft-Macro Placement Module Resynthesis Chip Layout Soft-Macro location

23. Soft-Macro Placement • Inputs: a set of soft-macros and the available area for soft macros. • Outputs: the locations of all soft macros. • Algorithm: • 1st step: force-directed-based placement. • 2nd step: line-sweep-based soft-macro assignment.

24. IO HM IO IO HM IO Force-directed-based Placement

25. HM HM IO IO IO IO SM4 SM2 SM3 HM HM HM HM SM1 IO IO IO IO HM HM Force-directed-based Placement

26. SM area Soft-Macro Area Extraction IO HM IO IO HM IO

27. SM2 & SM4 SM area Sweeping-based Soft-Macro Assignment ( Y direction ) Y SM1 SM1 HM SM area SM2 X SM4 HM SM3 SM3

28. Sweeping-based Soft-Macro Assignment Sweeping-based Soft-Macro Assignment X direction Y SM1 HM SM1 SM4 SM2 SM area SM2 X SM4 HM SM3 SM3

29. The Proposed Flow HDL Description P&R Routed database RTL netlist RC Extraction & Delay Calculation HDL Synthesis Timingconstraint SDF file Soft-Macro Formation Soft-Macro Formation Post-layout Timing Analysis Soft-Macro group Block Placement Timing Ok & no more area improvement Hard macro location Yes Yes No Soft-Macro Placement Module Resynthesis Chip Layout Soft-Macro location

30. The Proposed Flow HDL Description P&R Routed database RTL netlist RC Extraction & Delay Calculation HDL Synthesis Timingconstraint SDF file Soft-Macro Formation Soft-Macro Formation Post-layout Timing Analysis Soft-Macro group Block Placement Timing Ok & no more area improvement Hard macro location Yes Yes No Soft-Macro Placement Module Resynthesis Chip Layout Soft-Macro location

31. The Proposed Flow HDL Description P&R Routed database RTL netlist RC Extraction & Delay Calculation HDL Synthesis Timingconstraint SDF file Soft-Macro Formation Soft-Macro Formation Post-layout Timing Analysis Soft-Macro group Block Placement Timing Ok & no more area improvement Hard macro location Yes Yes No Soft-Macro Placement Module Resynthesis Chip Layout Soft-Macro location

32. The Proposed Flow HDL Description P&R Routed database RTL netlist RC Extraction & Delay Calculation HDL Synthesis Timingconstraint SDF file Soft-Macro Formation Soft-Macro Formation Post-layout Timing Analysis Soft-Macro group Block Placement Timing Ok & no more area improvement Hard macro location Yes Yes No Soft-Macro Placement Module Resynthesis Chip Layout Soft-Macro location

33. The Proposed Flow HDL Description P&R Routed database RTL netlist RC Extraction & Delay Calculation HDL Synthesis Timingconstraint SDF file Soft-Macro Formation Soft-Macro Formation Post-layout Timing Analysis Soft-Macro group Block Placement Timing Ok & no more area improvement Hard macro location Yes Yes No Soft-Macro Placement Module Resynthesis Chip Layout Soft-Macro location

34. The Proposed Flow HDL Description P&R Routed database RTL netlist RC Extraction & Delay Calculation HDL Synthesis Timingconstraint SDF file Soft-Macro Formation Soft-Macro Formation Post-layout Timing Analysis Soft-Macro group Block Placement Timing Ok & no more area improvement Hard macro location Yes Yes No Soft-Macro Placement Module Resynthesis Chip Layout Soft-Macro location

35. Module Resynthesis • Slack Computation: • Calculate the slack value for each inter-macro signal path • Soft-Macro Resynthesis Candidate Selection: • If there exists a negative slack value of any soft-macro then pick the one with highest negative slack as the candidate to resynthesize using tightened timing constraint • If all timing satisfies the timing constraint then pick the one with highest positive slack value as the candidate to resynthesize using relaxed timing constraint

36. The Proposed Flow HDL Description P&R Routed database RTL netlist RC Extraction & Delay Calculation HDL Synthesis Timingconstraint SDF file Soft-Macro Formation Soft-Macro Formation Post-layout Timing Analysis Soft-Macro group Block Placement Timing Ok & no more area improvement Hard macro location Yes Yes No Soft-Macro Placement Module Resynthesis Chip Layout Soft-Macro location

37. The Proposed Flow HDL Description P&R Routed database RTL netlist RC Extraction & Delay Calculation HDL Synthesis Timingconstraint SDF file Soft-Macro Formation Soft-Macro Formation Post-layout Timing Analysis Soft-Macro group Block Placement Timing Ok & no more area improvement Hard macro location Yes Yes No Soft-Macro Placement Soft-Macro Placement Module Resynthesis Chip Layout Soft-Macro location

38. The Proposed Flow HDL Description P&R P&R Routed database RTL netlist RC Extraction & Delay Calculation HDL Synthesis Timingconstraint SDF file Soft-Macro Formation Soft-Macro Formation Post-layout Timing Analysis Soft-Macro group Block Placement Timing Ok & no more area improvement Hard macro location Yes Yes No Soft-Macro Placement Module Resynthesis Chip Layout Soft-Macro location

39. The Proposed Flow HDL Description P&R Routed database RTL netlist RC Extraction & Delay Calculation RC Extraction & Delay Calculation HDL Synthesis Timingconstraint SDF file Soft-Macro Formation Soft-Macro Formation Post-layout Timing Analysis Soft-Macro group Block Placement Timing Ok & no more area improvement Hard macro location Yes Yes No Soft-Macro Placement Module Resynthesis Chip Layout Soft-Macro location

40. The Proposed Flow HDL Description P&R Routed database RTL netlist RC Extraction & Delay Calculation HDL Synthesis Timingconstraint SDF file Soft-Macro Formation Soft-Macro Formation Post-layout Timing Analysis Post-layout Timing Analysis Soft-Macro group Block Placement Timing Ok & no more area improvement Hard macro location Yes Yes No Soft-Macro Placement Module Resynthesis Chip Layout Soft-Macro location

41. The Proposed Flow HDL Description P&R Routed database RTL netlist RC Extraction & Delay Calculation HDL Synthesis Timingconstraint SDF file Soft-Macro Formation Soft-Macro Formation Post-layout Timing Analysis Soft-Macro group Block Placement Timing Ok & no more area improvement Timing Ok & no more area improvement Hard macro location Yes Yes No Soft-Macro Placement Module Resynthesis Chip Layout Soft-Macro location

42. Yes The Proposed Flow HDL Description P&R Routed database RTL netlist RC Extraction & Delay Calculation HDL Synthesis Timingconstraint SDF file Soft-Macro Formation Soft-Macro Formation Post-layout Timing Analysis Soft-Macro group Block Placement Timing Ok & no more area improvement Hard macro location Yes Yes No Soft-Macro Placement Module Resynthesis Chip Layout Soft-Macro location

43. The Proposed Flow HDL Description P&R Routed database RTL netlist RC Extraction & Delay Calculation HDL Synthesis Timingconstraint SDF file Soft-Macro Formation Soft-Macro Formation Post-layout Timing Analysis Soft-Macro group Block Placement Timing Ok & no more area improvement Hard macro location Yes Yes No Soft-Macro Placement Module Resynthesis Chip Layout Chip Layout Soft-Macro location

44. The Experiment Environment Setup HDL Description Avant!(P&R) P&R Routed database RTL netlist Avant!(STAR-RC) Avant!(STAR-DC) RC Extraction & Delay Calculation Synopsys HDL Synthesis Timingconstraint SDF file Soft-Macro Formation Synopsys (Design Time) Post-layout Timing Analysis Soft-Macro group Cadence (Block Placement) Block Placement Timing Ok & no more area improvement Hard macro location Yes Yes No Soft-Macro Placement Module Resynthesis Chip Layout Soft-Macro location

45. Benchmarks

46. Results (Ind1 @ TSMC 0.5um)

47. Results (Ind2 @ TSMC 0.5um)

48. Results (Ind3 @ TSMC 0.5um)

49. Results (Ind2 @ 0.25um)

50. Results (Ind2 @ 0.5um) The original critical path and new critical path of Ind2 using the 0.5um library after two resynthesis iterations