Assertion Based Verification of Mixed Signal Designs

1. Assertion Based Verification of Mixed Signal Designs Sanjib Kumar Das Roll No: 03CS1018 Under Supervision of Dr. Pallab Dasgupta Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur

2. Organization The Motivation Work Done Problem Formulation AMS_SVA language AMS_SVA Synth Tool AMS_SVA_Verify Tool Results

3. Contents The Motivation Work Done Problem Formulation AMS_SVA language AMS_SVA Synth Tool AMS_SVA_Verify Tool Results

4. The motivation • Today, verification consumes 70% of the time in VLSI design cycle. Bugs are costlier than transistors. • Assertion based verification (ABV) • An assertion is a formal specification of a property that the designer wants to verify on the design • Static ABV • Also known as FPV • Small design blocks • Dynamic ABV • Simulation based • More scalable

5. The motivation (contd.) • Most of the current ABV techniques are confined only to digital domain. Several Languages like SVA, Sugar etc. exist to specify assertions over Digital circuits. • This project aims to develop a prototype tool forAssertion Based Verification of Mixed Signal Circuits. • Our target circuits are mixed signal circuits with a large digital component (big D) and a small but significant analog component (small A). Eg: - A battery charger

6. Organization The Motivation Work Done Problem Formulation AMS_SVA language AMS_SVA Synth Tool AMS_SVA_Verify Tool Results

7. Work done so far A brief summary of the main contributions : • AMS_SVA,based on SystemVerilog Assertions(SVA) was presented. • supports electrical signals (as in Verilog AMS) and predicates over electrical signals. • Expressiveness of AMS_SVA • considering the design of a battery charger and the associated properties on it. • Presentation of a tool, AMS_SVA_Synth • synthesizes properties specified in AMS_SVA into monitors in Verilog AMS and Verilog. These monitors, when co-simulated with the design, dynamically check whether the properties match or fail.

8. Organization A Motivation Related Works Work Done Problem Formulation AMS_SVA language AMS_SVA Synth Tool AMS_SVA_Verify Tool Results

9. An overview How to express these properties formally? How to check these properties? Mixed Signal Design Under Test English Language specifications New AMS_SVA assertions AMS_SVA Language Property monitors AMS_SVA_Synth Tool Match / Fail

10. Problem Formulation • Given: A mixed signal design with a set of properties expressed in natural language like English. • Express these properties as a set of AMS_SVA assertions. • Generate a set of Verilog-AMS monitors for the analog blocks in these assertions. • Instantiate the property monitors in the test bench and simulate the design with the properties. • Report the match/fail corresponding to each of the properties.

11. Organization A Motivation Work Done Problem Formulation AMS_SVA language AMS_SVA Synth Tool AMS_SVA_Verify Tool Results

12. AMS_SVA Language • An Assertion language with support for writing predicates over electrical signals like voltage and current. • Modeling the new language on SVA due to following reasons. • Verification engineers conversant with SVA will find easy to relate with the new language. • We had a tool SVA_Synth to synthesize Verilog monitors with SVA assertions.

13. Expressiveness of SVA • SVA is purely for digital designs. • Sequence Expressions are the building blocks • define the temporal properties of a design. • Eg: A property on an arbiter Whenever request line r1 goes high the grant line g1 must be asserted for the next two cycles. LTL : G[r1 =>Xg1 ^ XXg2] SVA: property p1 @posedge(clk) r1|##1 g1 ##1 g1 endproperty ##1 is equivalent to the next(X) operator of LTL.

14. Expressiveness of AMS_SVA • A mixed-signal design with a well defined controller state machine involves two types of properties • State property • Analog properties that characterize the analog behavior of the design at a given state of the controller • (fsm_state==on) |-> (V<=Vref + Vth) • Transition property • Specify the enabling condition of state transition of the controller • (fsm_state==on) && (V==Vref + Vth) |-> (fsm_state==off)

15. AMS_SVA • A new non-terminal called, ANAPROP is introduced in the grammar. • {V(B)>0.9},{I(x,y) < 0.3},{ddt(V(p1))} • A new operator called first_occurrence is added to specify properties like rise time, settling time etc. which are specified in terms of first occurrence of an event during the simulation run. • The operator is applicable over an ANAPROP. • Consider a property on an LCR circuit The voltage at port a should reach 90% of Vmax within n clock cycles from the time it crossed 10% of Vmax AMS_SVA assertion : first_occurrence(V(a) > 0.1*Vmax) |##[0:n](V(a) > 0.9 *Vmax)

16. Organization The Motivation Related Works Work Done Problem Formulation AMS_SVA language AMS_SVA Synth Tool AMS_SVA_Verify Tool Results

17. AMS_SVA_Synth Tool

18. Steps in the tool flow • Consider an AMS_SVA assertion P : ((V(X) >0.2) && a) ##[5:8]b) or ((V(X)<0.9)[*3:8]) |(I(X,Y) == 0) • Step 1: Identify the analog propositions and replace them by Boolean variables. • P’ : (v1 && a) ##[5:8]b) or v2[*3:8] | v3 • P’ is pure SVA. • v1,v2,v3 hold true when corresponding analog propositions are true. • GenSVA_ANALOG_assertions does this. • Step 2: Generate Verilog AMS monitors for the analog propositions. • Say mon1 for V(X) > 0.2V • module mon1(X,v1); input X; output v1; electrical X; always @(above(V(X)-0.2)) v1=1; always @(above(0.2-V(X)) v1=0; endmodule • GenANALOG_monitors does this.

19. Steps in the tool flow (contd..) • Step 3 : GenSVAmonitors genrates Verilog monitors for the SVA assertion in P’. This is done by a tool SVA_Synth developed in a previous work by Prof. P. Dasgupta et al. • This machine has the inputs a,b,v1,v2,v3 and asserts a match when P’ matches. • Step 4 :The interconnections are done and finally we have one monitor for one property. • Step5 : The monitors are instantiated in the design and simulaton is carried out. • So what is the drawback with this approach?

20. So where is the problem?? • The bottleneck in the previous tool is the use of SVA_Synth • There is no single simulation platform that supports both Verilog AMS and SVA. • Moreover, the instantiation of monitors and other steps are done manually. • Need for a push-button tool • The simulation platform on which we had mainly worked until now namely , Cadence AMS Designer supports only Verilog AMS and not SVA.VCS of Synopsis on the other hand supports SVA, but no Verilog AMS. • In our project we achieve the communication of the two environments which helps us in developing an enhanced automatic tool.

21. The VPI Interface of Verilog AMS • Provides routines which allow Verilog-AMS product users to access information contained in a Verilog-AMS design and allow facilities to interact dynamically with a software product. • Dynamic software product interaction is accomplished with a registered callback mechanism. • VPI callbacks must be registered by the user

22. VPI access to Verilog-AMS objects • Accessible Verilog-AMS HDL objects and simulation objects and their relationships and properties are described using data model diagrams in the LRM. • The data diagrams indicate the routines and constants which are required to access and manipulate objects within an application environment. • VPI routines provide access to objects in an instantiated Verilog-AMS design.

23. Writing Application Using VPI • Following steps need to be performed to write a C application and interface with Verilog simulator. • Writing a C function • Associating C Functions with a New System Task • Registering New System Tasks • Invoking System Tasks • In our project we made use of the VPI routines which would help us access the values of various signals in the DUT at each simulation step. • The details of these routines can be obtained from the Verilog AMS LRM.

24. SystemVerilog Direct Progamming Interface (SVDPI) • Counterpart of the VPI interface in Verilog AMS.However,its far more simpler and straightforward with its import/export methodolgy. • SVDPI allows Verilog code to call the names of C functions as if the function were a native Verilog task or function. This is done by importing the C function name into the Verilog language using a simple “import” statement. • Note: In fact, even importing is not required.Declaring the C function as extern and calling it from the Verilog code works!

25. The New tool : AMS_SVA_Verify

26. A note on the VAMS monitors • Important difference between the current and voltage monitors. • Current monitors on the same electrical connection must be placed in parallel • Voltage monitors must be placed in parallel. • Consider a hypothetical AMS_SVA assertion : (V(X,Y) >0.3V) && (V(X,Y) < 0.9V) | (I(X,Y) >0.3A) && (I(X,Y)< 0.9A) • This will result in 4 monitors : • V_mon1(X,Y,v1),V_mon2(X,Y,v2) • I_mon1(X,Y,i1),I_mon2(X,Y,i2) • If we instantiate these monitors as above in the test bench we will have serious problems for the current monitors, because this would mean placing the current monitors in parallel • So, for current monitors, need to create a dummy node on the branch and instantiate as : I_mon1(X,dummy,i1) and I_mon2(dummy,Y,i2)

27. Results • The tool has been tried on simple but representative designs • An arbiter circuit( no AMS component) • An LCR circuit( where rise time properties were verified using the first_occurrence) • A battery charger example ( an excellent example of mixed signal design)

28. Results ( Contd…) • The real result lies in running the tool on large industrial designs. It is evident that for those large designs where simulation time is very large the overhead for the monitors would be negligible • Other results in the form of time break-up for the various phases can also be generated. This would help us determine the bottleneck.

29. Conclusion and Future work • We have presented a novel methodology for the verification of mixed signal designs. There are no such tools currently existing in the industry. This tool has the potential to meet the industry requirements after a bit of fine tuning. • The main assessment of the tool’s performance will be trying it on a large industrial design. • We can make our AMS_SVA language richer by incorporating features such as • Multiple clock expressions • Local variables

30. Thank you