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Verification of complex mixed signal ASICs

System-Verilog and UVM mini workshop 14 th November 2013. Verification of complex mixed signal ASICs. T . Hemperek. Moore's law in HEP. Switch to big “D”, little “A”. Same pattern for HEP. Verification. Verification plan Simulation Assertion based verification Formal verification

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Verification of complex mixed signal ASICs

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  1. System-Verilog and UVM mini workshop 14thNovember 2013 Verification of complex mixed signal ASICs T. Hemperek

  2. Moore's law in HEP

  3. Switch to big “D”, little “A” Same pattern for HEP

  4. Verification • Verification plan • Simulation • Assertion based verification • Formal verification • Mixed signal verification • FE-I4

  5. Verification Plan

  6. Simulation – Unified Verification Methodology

  7. Assertions based verification A pattern describes a proven solution to a recurring design problem // A start can only occur after a grant for an active requestassert property (@(posedgeclk) disable iff (~rst_n)req[*1:8] ##0 grant ##1 req |-> start);

  8. Formal verification // SystemVerilogAssertion propertyp_arb; @(posedgeclk) req|=> ##[0:2] gnt; endproperty assertproperty (p_arb);

  9. Static verification checking and simulation

  10. Metric Driven Verification

  11. MS Verification

  12. Accuracy versus performance Source: Cadence Design Systems

  13. Modeling feature chart

  14. FE-I4 Top View ANALOG ARRAY (digital part) DIGITAL ARRAY END OF COLUMN END OF CHIP COMMAND DECODER PLL PLL REGISTER MEMORY DATA OUTPUT - verilog model - Implementation (rtl/gate)

  15. FE-I4 Verification environment For FE-I4 we heve 4 OVC: - PIX - CMD - REVEIVE - MANUAL

  16. Questions?

  17. UVM register model

  18. System Verilog

  19. A UVM layer for PyHVL http://www.fivecomputers.com/a-uvm-layer-for-pyhvl.html

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