Tackling Mixed-Signal System Design and Verification Challenges Using MathWorks Tools

1. Tackling Mixed-Signal System Design and Verification Challenges Using MathWorks Tools Corey Mathis Industry Marketing Manager Mike Mulligan, Ph.D. Senior Applications Engineering Manager

2. Introductions: MathWorks Mike Mulligan, Ph.D Senior AE Manager Corey Mathis Industry Marketing

3. Agenda

4. Overview of Mixed-Signal Design and Verification Challenges

5. Mixed-Signal Integrated Circuits • Analog and digital circuits integrated on the same chip • A/d, a/D, A/D • ADC/DAC, PLL, Power supplies, MEMs, Sensors, … (control systems based on feedback loops + digital signal processing) The analog part of a typical mixed-signal SoC is typically a small fraction of the total number of devices; 15,000 to 25,000 devices seems a common range for the number of analog devices. (*) … by the end of this decade it is estimated that over 80% of all the silicon (by volume) shipped in the world will have at least 20% of silicon area dedicated to analog and RF functions (**) (*) CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design, Leenaerts, Gielen, Rutenbar (**) Entering the Golden Age of Mixed-Signal Semiconductors, R. Subramanian, CEO, Berkeley Design Automation

6. Who Design Mixed-Signal ICs? • (Large) semiconductorscompanies: • Intel, Texas Instruments, Freescale Semiconductor, Maxim Integrated Products, Analog Devices, NXP Semiconductors, Infineon Technologies, STMicroelectronics, Renesas, Fujitsu … • (Small) fabless design houses: • Dialog Semiconductor, Catena, Axiom IC, M4S, Ansem IC, Easics, IC Sense, SystematIC… Figures such as a $1 million plus to buy one mask set and $10 million to complete an IC design clearly position ASIC design as only a rich person’s game. However, these figures are only for leading-edge processes that are cost-justified by the ability to integrate tens of millions of transistors onto one die. But for analog and mixed-signal ICs, the picture can be very different(*) …older processes are more reliable, have stable PDK (Process Design kit) and can be used for MPW to share costs even further and admit smaller production batches. (*) Away from the Bleeding Edge Life is Good, P. Double, Founder and Managing Director, EDA Solutions

7. Mixed-Signal ICs are Everywhere • Market driven by many application fields • automotive, consumer, computer, communications, industrial automation, defense, medical, … … it is not so much a result of a killer application, but that of advancing technology or multiple next generation markets, where digital signal processing is showing up in everything from cars to home security systems. This shift from “ killer application” to next generation markets has been called many things, including “convergence,” but really the greatest impact has come from the digitization of content (so far, the most efficient way to store information). In order for digitized content to be used, it needs to be translated into a form useful and convenient for human beings. (*) (*) Real World Signal Management Drives $50 Billion Mixed-Signal Market, an FSA Forum special report, Data Beans

8. The Internet of Things Requires Mixed-Signal Systems “There are already more Internet-connected devices on the planet than people, and industry experts predict that the number of connected devices for the IoT will top 15 billion nodes by 2015 and reach 50 billion nodes by 2020. Many of those nodes will require energy-friendly ARM-based MCUs and wireless systems-on-chip (SoCs) designed to achieve current consumption as low as 100 µA per megahertz.” – Tyson Tuttle, CEO, Silicon Labs Addressing MCU Mixed Signal Design Challenges, D. Soubra – ARM, J. Rosenberg – ARM, M. Nizic- Cadence

9. Mixed-Signal IC Design Challenges • Long design cycles • Lack of analog synthesis • Hard to find design experts (highly needed) • Infinite design space • Tight dependency from the silicon process • Second and third order effects are part of the design • Hard to build IP libraries for general re-use • Process retargeting is difficult: Moore’s Law does not apply Unlike digital circuits, analog circuits exploit rather than avoid the physics of the fabrication process … analog circuits resist technology migrationand retargeting (*) Analog design is an art as much as a science … it takes 5 to 10 years to train strong designers …Semiconductor companies typically find only one AMS designer for every 200 digital designers. (**) (*) CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design, Leenaerts, Gielen, Rutenbar (**) Specification-driven design environment is key to productivity gains in analogdesign, white paper, Cadence

10. Mixed-Signal IC Design and Verification Trends • A/MS Design requires a collaborative environment • Analog and digital are no longer separate worlds • A/MS Verification requires multi-domain high-level models • Functionality must be verified at the system-level before tape-out According to industry estimates, more than 60 percent of SoC design re-spins at 45 nanometers and below are due to mixed-signal errors. A re-spin may cost an extra 5 to 10 million dollars and an 8 to 10 week delay in a product rollout, with potentially disastrous consequences. Ed Petrus, Director of Custom Automation, Mentor Graphics March, 2013 ISQED2013

11. The MS Verification Challenge To enable top-level simulations of mixed-signal SOCs we need models of analog blocks Digital abstractions (Real Number Modeling) are needed to allow for high functional verification coverage Analog designers rarely have knowledge of behavioral modeling languages – hesitant to learn Tim Guglielmo, Subodh Reddy, Maxim Integrated MladenNizic, Eng. Director, Mixed-signal Solutions, Cadence, September 20, 2012

12. Models are Slow and Hard to Build Mixed-signal SOC verification using analog behavioral models, Qi Wang, Cadence Design Systems -August 21, 2012

13. Which Languages Do A/MS Designers Speak? • Spice • VerilogAMS / VHDL-AMS • SystemVerilog • SystemC • C/C++ • Verilog / VHDL • MATLAB / Simulink Emerging Solutions for Mixed-Signal SoCVerification, K. Karnane, Cadence Design Systems

14. MathWorks Tools Integrate Your Design Flow • Multi-domain algorithm development • Integration with sensors and actuators • Design of control logic (HW/SW) • Refinement of the models (spice-like, finite precision) SPECIFICATION DESIGN Algorithms Fixed-Point Digital Analog Physical • Verification • Co-simulation with 3rd party tools • Testbench and IP generation • Integration with test and measurement equipment • Hardware in-the-loop simulation TEST & VERIFICATION IMPLEMENTATION VHDL, Verilog Spice-like FPGA ASIC ASIC SMPS • Implementation and prototyping • C code generation • Synthesizable HDL code generation INTEGRATION

15. Save 30% of Overall Development Time(and Improve Quality, Reduce Re-Spins, etc.)* (*) MathWorks study done across companies developing mixed-signal systems in The Netherlands and Germany

16. Why A/MS Designers Use MathWorks Tools? Focus on system-level modeling and algorithm development • Large set of libraries and functions to rapidly design and test new algorithms • Span across multiple domains (analog, digital, RF, Hardware / Software) • Behavioral modeling is easy • Simulation is fast • Analysis is powerful • Early algorithmic integration and verification • Find errors early: single platform for system-level multi-domain modeling across an entire organization • Rapid design iterations • Designers have lots and lots of good ideas: kill good ideas quickly and focus on great ones • Focus on innovation • Increase reuse instead of re-inventing the wheel

17. Three Good Reasons why Simulink and MATLAB Should be on the Desktop of Every A/MS Designer • Behavioral modeling is easy • Simulation is fast • Analysis is powerful

18. Three Good Reasons why Simulink and MATLAB Should be on the Desktop of Every A/MS Architect • Behavioral modeling is easy • Simulation is fast • Analysis is powerful Model an Agile RF Transceiver

19. Anti-lock braking system sensors. Allegro MicroSystems Reduces Anti-Lock Braking System Sensor Development Time • Challenge Accelerate the development of next-generation Hall-effect sensors for anti-lock braking systems Solution • Use Simulink and SimPowerSystems to quickly and accurately design and simulate electrical and logical models and simulate new sensor systems • Results • Time-to-market shortened • Risk of algorithm flaws reduced • Tests developed before sensor manufacturing “Using MathWorks tools, we identified the best algorithm choice. Because the model ran much faster than our circuit simulator, we caught implementation errors much quicker and shortened our time to market.” Cory VoisineAllegro MicroSystems Anti-lock braking system sensors.

20. Semtech Speeds Development of Digital Receiver FPGAs and ASICs • Challenge • Accelerate the development of optimized digital receiver chains for wireless RF devices Solution • Use MathWorks tools for Model-Based Design to generate production VHDL code for rapid FPGA and ASIC implementation Results • Prototypes created 50% faster • Verification time reduced from weeks to days • Optimized, better-performing design delivered The Semtech SX1231 wireless transceiver. “Writing VHDL is tedious, and the handwritten code still needs to be verified. With Simulink and HDL Coder, once we have simulated the model we can generate VHDL directly and prototype an FPGA. It saves a lot of time, and the generated code contains some optimizations we hadn’t thought of.” Frantz PrianonSemtech

21. Why Should You Consider MathWorks Tools? • Make the design process more productive and creative • No need to re-invent the wheel • Agile management of changing specifications • Achieve early verification by sharing models within the entire organization • Multi-domain modeling for early integration at the system-level • Co-simulation with third party software and hardware • Share your hardware models with providers / customers • Executable specifications reduce errors and improve quality

22. Modeling and Simulation for Mixed-Signal Systems

23. Mixed-Signal Design and Verification Challenges SPECIFICATION Limited analog design abstractions DIGITAL DESIGN ANALOG DESIGN IMPLEMENTATION Specification isolated from verification Limited analog/digital links IMPLEMENTATION Difficult design trade-offs VHDL, Verilog Spice-like TEST & VERIFICATION Disconnected teams Slow design iterations PROTOTYPE / INTEGRATION

24. Focus on Algorithm Design Rapid design construction SPECIFICATION Easier analog modeling ANALOG & DIGITAL DESIGN Specification isolated from verification Limited analog/digital links IMPLEMENTATION IMPLEMENTATION VHDL, Verilog Spice-like TEST & VERIFICATION Disconnected teams Slow design iterations PROTOTYPE / INTEGRATION

25. Anticipate Impairments at the System-Level Rapid design construction SPECIFICATION Easier analog modeling ANALOG & DIGITAL DESIGN Fixed-Point Physical Specification isolated from verification Multi-domain simulation IMPLEMENTATION IMPLEMENTATION VHDL, Verilog Spice-like TEST & VERIFICATION Disconnected teams Rapid design iterations PROTOTYPE / INTEGRATION

26. Continuous Verification Rapid design construction SPECIFICATION Easier analog modeling ANALOG & DIGITAL DESIGN Integrated specification Multi-domain simulation TEST & VERIFICATION IMPLEMENTATION IMPLEMENTATION VHDL, Verilog Spice-like Improved team communication Rapid design iterations PROTOTYPE / INTEGRATION

27. Simulink for Analog/Mixed Signal Unique advantages • Model continuous-time and discrete-time components together • Express analog filters as Laplace transforms or RLC circuits • Variable step ODE solvers • Zero crossings and discontinuities • Feedback control loops, VCOs, PLLs

28. Mixed-Signal Library(download from mathworks.com)

29. Generic SERDES Implementation Encoded Transmitted Data + FFE CTLE CDR DFE Backplane + Crosstalk

30. Typical SERDES Design Workflow • Time-domain characterization of the channel • Design of analog and digital equalizers • Simulation of the system performance including timing impairments 2 1 3

31. 1. Time-domain Characterization of the Channel

32. Multi-port S-Parameters Characterization Single-ended N-port S-parameters: • VNA measurement • Full-wave EM simulation

33. Creating a Simulink Block from S-parameter Channel Data

34. 2. Design of Analog and Digital Equalizers

35. Design of Analog Equalizer (CTLE) • Block diagram of an individual bandpass filter: • Cascade of filters with inverted frequency response to that of the backplane Source: “A LOW-POWER GIGABIT ETHERNET ANALOG EQUALIZER,” Amini, Pezhman and Shoaei, Omd. IEEE 2001 International Symposium on Circuits and Systems, pp. 176-179 vol.1

36. Design of Digital Equalizers • Feed-Forward Equalizer (FFE) • Decision Feedback Equalizer (DFE) • Use adaptive filters to compute the filter order and the coefficients • The designed filters are synthesizable NRZ source FFE Backplane CTLE DFE

37. Calculate the Coefficients for the FFE Recursive Least Square Adaptive Filter

38. Design Elaboration with Circuit Elements

39. 3. Simulation of the System Performance Including Timing Impairments

40. Post Processing Simulink Data With MATLAB:Bathtub Curve Generation

41. Further Elaborations:Multi Port Channel, Transceiver Models

42. Fixed-point filter design • Fixed-point refinement of digital components • Fixed-point design • Fixed-point simulation • Fixed-point optimisation

43. C Code Generation • Generate C/C++ code for implementation, or deployment to other environments

44. HDL Code Generation • Generate VHDL or Verilog for Implementation

45. Fujitsu Develops and Tests State-of-the-Art 40 Gbps Optical Transponder • Challenge Develop a 40 Gbpsserializer/deserializer integrated circuit for an optical transponder Solution • Use Simulink to model and simulate key components of the design, and use MATLAB and Instrument Control Toolbox to automate chip testing and characterization Results • First-silicon-success for components verified inSimulink • Faster verification of mixed-signal designs • Test time reduced by 90% SERDES chips mounted on inert substratefor testing. “By including circuit-level simulation results in our Simulink models we can simulate millions of cycles with the accuracy needed to account for noise and other transient effects. Simulink is the only tool fast enough for our jitter-tolerance simulations.” William WalkerFujitsu Laboratories of America Link to user story

46. Keeping Everyone in the Loop: Designing a Better Analog-to-Digital Converter • Challenge • Create and evaluate alternative designs for a novel ADC architecture Solution Build a system-level model in Simulink and simulate multiple designs Results • Collaboration between geographically separated teams enabled • Multiple design ideas rapidly explored • Circuit-level design streamlined Time-encoded ADC test chip. • “Simulink enables us to rapidly simulate loops, making it a great choice for fast mixed-signal system simulation.” • Dietmar Sträussnigg • Infineon Technologies Link to article

47. Top-Down Design for Mixed-Signal Systems • Build a behavioral model to capture your requirements in an executable specification • Progressively refine the model using simulation results to inform your design choices • Connect to EDA tools for implementation in hardware • Validate your design throughout the process using the same testbench SPECIFICATION DESIGN Algorithms Fixed-Point Digital Physical Analog TEST & VERIFICATION IMPLEMENTATION VHDL, Verilog Spice-like FPGA ASIC ASIC SMPS INTEGRATION

49. Algorithm Implementation and Functional Verification

50. HDL Coder Generation of synthesible RTL HDL Support for MATLAB Simulink Stateflow Workflow Advisor Guides through process Preparing model for generation of HDL Configuring HDL Generation options Integratedswith synthesis tools for timing annotation on model Configurations for turnkey FPGA targets and IP Core generation Generation of HDL Source Code Algorithmic System-level Testbench Algorithm DataSource ComponentModel EnvironmentModel Analysis ComponentModel HDL Coder RTL HDL(VHDL, Verilog)