1 / 22

4bit-ALU (Arithmetic Logic Unit)

4bit-ALU (Arithmetic Logic Unit). Lam Nguyen Vinh Nguyen The Dao Advisor: Dr. David Parent Date: 12/05/05. Agenda. 1. Abstract 2. Introduction - Why? - Background Information 3. Project Summary - Schematic - Layout

Audrey
Download Presentation

4bit-ALU (Arithmetic Logic Unit)

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. 4bit-ALU(Arithmetic Logic Unit) Lam Nguyen Vinh Nguyen The Dao Advisor: Dr. David Parent Date: 12/05/05

  2. Agenda 1. Abstract 2. Introduction - Why? - Background Information 3. Project Summary - Schematic - Layout - LVS report -Longest Path Calculations -Lessons Learned 4. Summary 5. Acknowledgements

  3. Abstract Our designed project 4-ALU performs the following functions: • AND • OR • XOR • ADDER Area = 390µm×590µm =0.23µ m2

  4. Introduction • ALU is a basic fundamental unit of any computing system. • Understanding how an ALU is designed and how it works is a benefit to build any advanced logic circuits. • Using this experience, we can have a basic to design a more complex IC.

  5. Project Details • Create Schematics and layouts for And, Or, Xor, Adder, flip-flop, and Mux in the Cadence tool. • Test the schematics by using test bench. • Create Schematic and layout for 1 bit ALU • Run DRC, extract and LVS for 1 bit ALU. • Connect Cout of the first bit to Cin of the second bit and continue to have 4 bit ALU. • Run the DRC, extracted LVS and simulation to check the final design.

  6. 1bit-ALU Logic Logic DFF DFF The design uses the concept of parallel operations.

  7. 4-to-1 Mux ALU handles two inputs of 4 bits each to produce a required output based on the output selection

  8. 4-1 Mux Wp = 9µ Wn = 4.5µ

  9. 4-1Mux Test Bench Time delay: τ = 0.5ns

  10. 1-bit Adder Wp = 7.8µ Wn = 9µ

  11. 4-bit Full Adder Time delay τ = 1.5ns

  12. DFF Layout

  13. DFF Test Bench Time delay τ = 1.2ns

  14. Longest Path Calculations

  15. 4-ALU Schematic

  16. 4-ALU Layout

  17. Schematic Test Bench

  18. LVS

  19. Simulation Select S0 =1 and S1=1 to have the longest path

  20. Lessons Learned • Using Cadence tool • Designing an integrated circuit to met a specification. • Fixing errors from LVS report and extracted schematic file. • Using a same height for each layout cell to reduce the area.

  21. Summary • Our designed 4-bit ALU can operate for the following operations: And, Or, Xor, Add • Our project has 372 transistors and 20 terminals. • The delay propagation is 5ns. • Area = 390µm×590µm =0.23µ m2

  22. Acknowledgment • Thanks to professor David Parent for teaching and helping us throughout this project. • Thanks to Cadence Design Systems for VLSI Lab.

More Related