COMP541 Memories, Part I

1. 1 COMP541Memories, Part I Montek Singh Feb 27, 2007

2. 2 Topics Overview of Memory Types ROMs: PROMs, FLASH, etc. RAMs Random-Access Memory (RAM) Static today Dynamic next

3. 3 Properties of Memory What would you want?

4. 4 Non-Volatile Memory Technologies Mask (old) Fuses (old) Electrically erasable

5. 5 Details of ROM Memory that is permanent k address lines 2k items n bits

6. 6 Notional View of Internals

7. 7 Programmed Truth Table

8. 8 Resulting Programming In truth, they�re laid out in 2D (row, col)

9. 9 Mask ROMs Oldest technology Originally �mask� used as last step in manufacturing Specify metal layer (connections) Used for volume applications Long turnaround Used for applications such as embedded systems and, in the old days, boot ROM

10. 10 Programmable ROM (PROM) First ones had fusible links High voltage would blow out links Fast to program Single use

11. 11 UV EPROM Erasable PROM Common technologies used UV light to erase complete device Took about 10 minutes Holds state as charge in very well insulated areas of the chip Nonvolatile for several (10?) years

12. 12 EEPROM Electrically Erasable PROM Similar technology to UV EPROM Erased in blocks by higher voltage Programming is slower than reading Some called flash memory Digital cameras, MP3 players, BIOS Limited life Some support individual word write, some block One on Xess board has 5 blocks Has a boot block that is carefully protected

13. 13 Random Access Memories So called because it takes same amount of time to address any particular location This is not quite true for modern DRAMs First look at asynchronous static RAM Ones on Xilinx are synchronous Data available at clock edges, like registers

14. 14 Simple View of RAM Of some word size n Some capacity 2k k bits of address line Maybe have read line Strictly speaking may not need Have a write line

15. 15 1K x 16 memory Variety of sizes From 1-bit wide Issue is no. of pins Memory size often specified in bytes This would be 2KB memory 10 address lines and 16 data lines

16. 16 Writing Sequence of steps Setup address lines Setup data lines Activate write line (maybe a pos edge)

17. 17 Reading Steps Setup address lines Activate read line Data available after specified amt of time Some use a clock

18. 18 Chip Select Usually a line to enable the chip Why?

19. 19 Writing

20. 20 Reading

21. 21 Static vs Dynamic RAM SRAM vs DRAM DRAM stores charge in capacitor Disappears after short period of time Must be refreshed SRAM easier to use Uses transistors (think of it as latch) Faster More expensive per bit Smaller sizes

22. 22 Structure of SRAM Control logic One memory cell per bit Cell consists of one or more transistors Not really a latch made of NANDs/NORs, but logically equivalent

23. 23 Bit Slice Cells connected to form 1 bit position Word Select gates one latch from address lines Note it selects Reads also B (and B�) set by R/W, Data In and BitSelect Funny thing here when you write. What is it?

24. 24 Bit Slice can Become Module Basically bit slice is a X1 memory Next

25. 25 16 X 1 RAM Now shows decoder

26. 26 Row/Column If RAM gets large, there is a large decoder Also run into chip layout issues Larger memories usually �2D� in a matrix layout Next Slide

27. 27 16 X 1 RAM as 4 X 4 Array Two decoders Row Column Address just broken up Not visible from outside on SRAMs

28. 28 Change to 8 X 2 RAM Minor change in logic Also pinouts What�s different?

29. 29 Realistic Sizes Imagine 256K memory as 32K X 8 One column layout would need 15-bit decoder with 32K outputs! Can make a square layout with 9-bit row and 6-bit column decoders

30. 30 SRAM Performance Current ones have cycle times in low nanoseconds (say 2.5ns) Used as cache (typically onchip or offchip secondary cache) Sizes up to 8Mbit or so for today�s chips

31. 31 RAM on FPGA Ours has 10 4Kb blocks for a total of 40Kbits They call it block RAM Can also use LUTs as RAM Block RAM: Two ports, and 5 possible layouts

32. 32 Using from Verilog Instantiate a block (here called R1) RAMB4_S8_S8 R1 (.DOA (data_a), .DOB (data_b), .ADDRA (addr_a), .ADDRB (addr_a), .CLKA (clk), .CLKB (clk), .DIA (data_in), .DIB (data_in), .ENA (ena), .ENB (enb), .RSTA (rsta), .RSTB (rstb), .WEA (wea), .WEB (web));

33. 33 Synthesizer can Infer Careful how you specify (see ISE/XST manual) module inferRAM(clk, addr, data, we); input clk; input [8:0] addr; // 512 locations output [7:0] data; // by 8 bits input we; reg [7:0] mem [511:0]; reg [8:0] ra; always @ (posedge clk) begin if(we) mem[addr] <= data; ra <= addr; end assign data = mem[ra]; endmodule

34. 34 Can Initialize Block RAM Have to do it two ways, one for simulator, another for hardware //synthesis attribute INIT_00 of R1 is "08192A3B4C5... total of 256 bits (64 hex characters)..." //synthesis attribute INIT_01 of R1 is "08192A3B4C5D6E7F08192A3B4C5D6E7F08192A3B4C5D6E7F08192A3B4C5D6E7F� // Up to INIT_0F Above is for hardware (next software)

35. 35 For Simulation //synopsys translate_off defparam R1.INIT_00 = 64'h08192A3B4C5D6E7F08192A3B4C5D6E7F08192A3B4C5D6E7F08192A3B4C5D6E7F; // 256-bit hex value defparam R1.INIT_01 = 64'h08192A3B4C5D6E7F08192A3B4C5D6E7F08192A3B4C5D6E7F08192A3B4C5D6E7F; // 256-bit hex value ... defparam R1.INIT_0F = 64'h08192A3B4C5D6E7F08192A3B4C5D6E7F08192A3B4C5D6E7F08192A3B4C5D6E7F; // up to INIT_0F //synopsys translate_on

36. 36 Look at Test Code A RAM example Posted online (under Labs) Note how memory values are specified Addresses go right-to-left, top-to-bottom See the Constraints Guide and Library manuals in Xilinx docs

37. 37 Wider Memory What if you don�t have enough bit width?

38. 38 Deeper Memory Adding chips to increase storage, but keep same width Need decoder

39. 39 Today Fast look at non-volatile memory Learned about Static RAM Specifics: synchronous RAM in FPGA Next: Dynamic RAM Complex, largest, cheap Much more trouble to use