1 / 19

Clock, Slow Control and ECS signals distribution in the Calorimeter Front-end Crate

Clock, Slow Control and ECS signals distribution in the Calorimeter Front-end Crate. Reminder Calorimeter Front-end Crate 3U and 6U Backplane Detail of each slot SLVS specification Clock distribution in Calorimeter Front-end Crate

desma
Download Presentation

Clock, Slow Control and ECS signals distribution in the Calorimeter Front-end Crate

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Clock, Slow Control and ECS signals distribution in the Calorimeter Front-end Crate Reminder Calorimeter Front-end Crate 3U and 6U Backplane Detail of each slot SLVS specification Clock distribution in Calorimeter Front-end Crate Slow Control and Detector Command (ECS) distribution in Calorimeter Front-end Crate Data LHCbCalorimeter upgrade meeting Olivier Duarte

  2. Calorimeter front-end crate LHCbCalorimeter upgrade meeting • 2 Backplanes (6U and 3U) • 6U backplane • Neighbours • L0 data • Delatcheur command • Crate Id • 3U Backplane • Power Supply • Clock distribution • TTC command (or Control command) • Slot Id • SPEC distribution

  3. 3U Backplane CROC Slot LHCbCalorimeter upgrade meeting • Connection between CROC and FEB Through 3U Backplanes • 1 differential pair between each slot (FEB or TVB) and CROC (type point 2 point) • 9 differentials pair common on all the slot inside the same crate (type bus)

  4. 3U Backplane FEB Slot LHCbCalorimeter upgrade meeting • Connection between CROC and FEB Through 3U Backplanes • 1 differential pair between each slot (FEB or TVB) and the CROC (type point 2 point) • 9 differentials peer common on all the slot inside the same crate (type bus)

  5. 6U Backplane slot organization LHCbCalorimeter upgrade meeting

  6. 6U Backplane CROC Slot LHCbCalorimeter upgrade meeting • Connection between CROC and FEB Through 6U Backplanes • 4 differentials pair between each slot (FEB or TVB) and the CROC (type point 2 point)

  7. 6U Backplane FEB slot E-Port LHCbCalorimeter upgrade meeting • Connection between CROC and FEB Through 6U Backplanes • 4 differentials pair between each slot (FEB or TVB) and the CROC (type point 2 point)

  8. 6U Backplane Validation slot E-Port LHCbCalorimeter upgrade meeting • Connection between CROC and FEB Through 6U Backplanes • 4 differentials pair between each slot (FEB or TVB) and the CROC (type point 2 point)

  9. SLVS specification LVDS 400mV SLVS specifications brief 2 mA Differential max Line impedance: 100 Ohm Signal: +- 200 mV Common mode ref voltage: 0.2V 1.2V SLVS 200mV 0.2V LHCbCalorimeter upgrade meeting Kostas Kloukinas’s slide • SLVS (Scalable Low Voltage Standard) • JEDEC standard: JESD8-13 • Differential voltage based signaling protocol. • Voltage levels compatible with deep submicron processes. • Typical link length runs of 30cm over PCB at 1Gbps. • Low Power, Low EMI • Application in data links for Flat Panel displays in mobile devices. • Mobile Pixel Link, MPL-2 (National semi.)

  10. Clock distribution in Calorimeter Front-end Crate through 3U Backplane • Pending question • Is it possible to use translator • SLVS <-> LVDS ? Or inside GBT ? • See CRT 758 data sheet E-Port E-Port Inside GBTX ?? E-Port E-Port Clk[0] E-Port E-Port LVS-SLVS translator New FEB One GBTX master E-Port E-Port SLVS-LVDS translator Clock_Feb(n) In Ref Clk[7:0] Clk manager Network Controller Network Controller General Ctrl General Ctrl Clk[7:0] In Ref Clk manager Buffer 2 bidirlink One waylink User Buses : User Buses : 17 E-Port SCA Max for 1 GBTX GBTX {I2C, //, SPI, JTAG, 12bADC, …} {I2C, //, SPI, JTAG, 12bADC, …} ACTEL FPGA (A3PE1500) 2 GBTX Analog FE part (8 Channels) GBTX E-Port SCA Uplink Uplink 3U Backplane CROC Slot 3U Backplane FEB Slot 4 GBTX (One way) Down- link Down- link E-Port SCA New CROC 1 SCA LHCbCalorimeter upgrade meeting • GBT on board • On new CROC board • 2 GBTX chip with bidirectional optical fiber • 1 SCA chip (CROC Ctrl/Cmd) • On the new Calorimeter FEB • 4 GBTX chip (one way) • 1 SCA chip (FEB Ctrl/Cmd)

  11. Slow Control distribution in Calorimeter Front-end Crate through 6U Backplane 6U Backplane CROC Slot E-Port E-Port Clk[0] E-Port One GBTX master E-Port SLVS-LVDS translator In Ref Clk[7:0] Clk manager Network Controller General Ctrl Buffer x (18) E-Port_TVB E-Port_FEB 2 bidirlink Translator SLVS-LVDS User Buses : GBTX FPGA, Buffer, … E-Port SCA _NewCROC {I2C, //, SPI, JTAG, 12bADC, …} 2 GBTX E-Port SCA E-Port SCA_NewCROC Uplink Down- link 4 pairs 1 free • Slow Control transmission • Translator with FPGA ? • 4 pairs available • GBT E-Port 3 pairs used • 1 pair free New CROC 1 SCA LHCbCalorimeter upgrade meeting

  12. Slow Control distribution in Calorimeter Front-end Crate through 6U Backplane E-Port E-Port LVS-SLVS translator New FEB E-Port E-Port Network Controller Clk[7:0] In Ref General Ctrl Clk manager 4 pairs 1 free User Buses : ACTEL FPGA (A3PE1500) {I2C, //, SPI, JTAG, 12bADC, …} Analog FE part (8 Channels) GBTX Uplink 4 GBTX (One way) Translator SLVS-LVDS Down- link E-Port SCA FPGA, Buffer, … 6U Backplane FEB Slot • Slow Control transmission • Translator with FPGA ? • 4 pairs available • GBT E-Port 3 pairs used • 1 pair free LHCbCalorimeter upgrade meeting

  13. ECS commande (Channel B, Rst, …) distribution in Calorimeter Front-end Crate - through 3U Backplane • ECS cmd transmission • Used the same way (pins) as currently ! E-Port E-Port LVS-SLVS translator New FEB E-Port E-Port E-Port E-Port E-Port E-Port Clk[7:0] In Ref Clk manager Clk[0] Network Controller Network Controller General Ctrl General Ctrl SLVS-LVDS translator ?? Buffer In Ref Clk[7:0] Clk manager ACTEL FPGA (A3PE1500) Analog FE part (8 Channels) GBTX User Buses : User Buses : {I2C, //, SPI, JTAG, 12bADC, …} {I2C, //, SPI, JTAG, 12bADC, …} x (18) 4 GBTX (One way) E-Port_TVB E-Port_FEB 2 bidirlink Translator SLVS-LVDS Translator SLVS-LVDS GBTX Uplink Uplink E-Port SCA FPGA, Buffer, … E-Port SCA _NewCROC FPGA, Buffer, … 2 GBTX 3U Backplane CROC Slot Down- link Down- link E-Port SCA E-Port SCA_NewCROC 3U Backplane FEB Slot New CROC 1 SCA LHCbCalorimeter upgrade meeting

  14. Data 16 FEB E-Port E-Port LVS-SLVS translator E-Port New FEB E-Port Network Controller General Ctrl Clk[7:0] In Ref Clk manager User Buses : 4 One waylink per FEB ACTEL FPGA (A3PE1500) {I2C, //, SPI, JTAG, 12bADC, …} Analog FE part (8 Channels) GBTX Uplink 4 GBTX (One way) TELL 40 TELL 40 TELL 40 TELL 40 TELL 40 TELL 40 Translator SLVS-LVDS Down- link E-Port SCA FPGA, Buffer, … Readout Crate LHCbCalorimeter upgrade meeting • On New Calorimeter FEB • 4 GBTX chip (one way) • 1 SCA chip

  15. Summary • On the new CROC Board, 2 GBTX chip with bidirectional optical fiber and one SCA Chip. • On the new Calorimeter FEB, 4 GBTX (one way) and one SCA chip. • For the Clock distribution we will use SLVS <-> LVDS translator to transmit LVDS signals on 3U Backplane. Or is it possible with FPGA ? • Slow control distribution, 1 pair free. • (3 pair for each E-port, 4 pair on the 6U backplane !) • Transmission of the ECS command through the 3U backplane • Is it necessary to transmit SLVS on the backplane ?? LHCbCalorimeter upgrade meeting

  16. Spare LHCbCalorimeter upgrade meeting

  17. CRT758 Data Sheet LHCbCalorimeter upgrade meeting

  18. CRT758 Data Sheet (2) LHCbCalorimeter upgrade meeting

  19. Clock[7:0] External clock reference FEModule E – Port Phase - Shifter CLK Reference/PLL E – Port FEModule E – Port E – Port DEC/DSCR CDR Phase – Aligners + Ser/Des for E – Ports 80, 160 and 320 Mb/s ports CLK Manager SCR/ENC SER E – Port FEModule E – Port E – Port One 80 Mb/s port Control Logic Configuration GBT – SCA JTAG I2C Slave I2C Master E – Port I2C (light) JTAG Port I2C Port LHCb electronics, 14th June 2012

More Related