1 / 19

The Compatibility 6 Full-Adder Topologies with V DD Stacking

The Compatibility 6 Full-Adder Topologies with V DD Stacking. By Wenlu Sun & Jiyati Verma Thursday, December 1, 2011 ECE 6332 – VLSI Design Final Project Presentation. Overview. Purpose Full Adders Cadence Implementation Simulation Results Takeaways. V DD Stacking.

devi
Download Presentation

The Compatibility 6 Full-Adder Topologies with V DD Stacking

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. The Compatibility 6 Full-Adder Topologies with VDD Stacking By Wenlu Sun & Jiyati Verma Thursday, December 1, 2011 ECE 6332 – VLSI Design Final Project Presentation

  2. Overview • Purpose • Full Adders • Cadence Implementation • Simulation Results • Takeaways

  3. VDD Stacking • Noise Reduction attenuates Power Dissipated …Application of Stacked-VDD to adders

  4. Purpose • To minimize the fluctuation of Vmiddle • Which full adder topology does this the best? Can we make any generalizations in those decisions? Static Dynamic Transmission Gates

  5. Static Full Adders Static CMOS Mirror Adder

  6. Transmission Logic Adders Transmission Function Adder Transmission Gate Adder

  7. Dynamic NP CMOS Adders Standard Fare (#1) Suggested From a Paper(#2)

  8. (10) A0 FA0 S0 (01) B0 Cout,0 Cin,0 = A0 + – Vmiddle VDD (01) A1 FA1 S1 (10) B1 Cout,1 Cin,1 = A1 Cadence Implementation Claim: When inputs of FA0 and FA1 swing in opposite directions, then the greatest amount of noise occurs at the output causing the most imbalanced Vmiddle conditions.

  9. I/O for Mirror adder…

  10. Simulation Results

  11. Static CMOS Adder • 1.205 to 1.050 V. • Percents: 9.55% above and 4.55% below.

  12. Mirror Full Adder (MFA) • 1.148 to 0.985 V. • Percents: 4.36% above and 10.5% below.

  13. Transmission Function Adder (TFA) • 1.295 to 1.049 V. • Percents: 17.7% above and 4.63% below.

  14. Transmission Gate Adder (TGA) • 1.365 to 0.790 V. • Percents: 24.1% above and 28.2% below.

  15. Dynamic Adder #1 (Dyn1) • 1.335 to 0.7 V • Percents: 21.4% above and 36.4% below.

  16. Dynamic Adder #2 (Dyn2) • 1.406 to 0.861 V • Percents: 27.8% above and 21.7% below.

  17. All together now… • Static CMOS: +9.55%/-4.55% (Avg: 7.05%) • MFA: +4.36%/-10.5% (Avg: 7.43%) • TFA: +17.7%/-4.63% (Avg: 11.2%) • Dyn2: +27.8%/-21.7% (Avg: 24.8%) • TGA: +24.1%/-28.2% (Avg: 26.2%) • Dyn1: +21.4%/-36.4% (Avg: 28.9%)

  18. Takeaways / Conclusion • Static adders are the best! • Dynamic adders compromise stability for speed, which is needed in Stacked-VDDdesigns • Out of transmission logic adders, TFA does the best balancing of current

  19. Any Questions?

More Related