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This setup guide provides step-by-step instructions for testing the ADC12J4000 and TSW14J10 on the VC707 platform. The test conditions include using a single tone input with specific frequency settings. Learn how to configure the LMK, clock distribution modes, and lane rate. Follow the instructions to load preset values, set clock frequencies, and capture results using a 600MHz input tone. This comprehensive guide ensures accurate testing for optimal performance.
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Test Setup: • Single tone is given as input to the device. • Test conditions: • Fs = internal 4GHz • Fin = 600MHz • Dec 4 P54 mode • LMK = 2GHz, clock dist mode • VC707 Ref clock = 500MHz (/4 for LMK) • VC707 Core clock = 250MHz (/8 for LMK) • Lane Rate = 10G • V2p8 firmware
On ADC GUI, load the Preset 0 Frequency value as shown below
In Low Level View tab, set LMK04828 address 0x110 to 0x04 to set VC707 REFCLK = 500MHz
In Low Level View tab, set LMK04828 address 0x100 to 0x08 for VC707 Core CLK = 250MHz
Open HSDCD Pro, select “ADC12J4000_D4_DDR”, Enter “1G” for ADC Output Data Rate