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Asynchronous Circuit Verification and Synthesis with Petri Nets

This book explores the use of Petri nets as a formal model to specify causality, concurrency, and choice between events in asynchronous circuit verification and synthesis.

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Asynchronous Circuit Verification and Synthesis with Petri Nets

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  1. Asynchronous Circuit Verification and Synthesis with Petri Nets J. Cortadella Universitat Politècnica de Catalunya, Barcelona Thanks to: Michael Kishinevsky (Intel Corporation) Alex Kondratyev (The University of Aizu) Luciano Lavagno (Politecnico di Torino) Enric Pastor (Universitat Politècnica de Catalunya) Alex Taubin (The University of Aizu) Alex Yakovlev (University of Newcastle upon Tyne)

  2. Motivation • Interfaces are often asynchronous • Subsystems with different clocks often want to talk to each other • Self timing provides functional and temporal modularity • … and no clock skew, low power,low EMI, average performance, ...

  3. Why Petri nets ? • Formal model to specify causality, concurrency and choice between events • Simple enough to easily derive state-level information (logic synthesis) • Powerful enough to implicitly represent a large state space

  4. Outline • Design flow • Synthesis • Specification • State encoding • Logic decomposition • Synthesis of Petri nets • Formal verification

  5. Specification(STG) Reachability analysis State Graph State encoding SG withCSC Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist Design flow

  6. x x y y z z z+ x- x+ y+ z- y- Signal Transition Graph (STG)

  7. x y z z+ x- x+ y+ z- y-

  8. xyz 000 x+ 100 y+ z+ z+ x- 110 101 x- x+ y+ z- y- y+ z+ 001 111 y- y+ x- 011 z- 010

  9. xyz 000 x+ 100 y+ z+ Currentstate Nextstate 110 101 x- y- y+ z+ 001 111 y+ x- 011 z- Currentstate Nextstate 010 Synchronous Asynchronous

  10. xyz 000 x+ 100 y+ z+ 110 101 x- y- y+ z+ 001 111 y+ x- 011 z- 010 Next-state functions

  11. Next-state functions x y z

  12. Specification(STG) Reachability analysis State Graph State encoding SG withCSC Design flow Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist

  13. Bus Data Transceiver DSr LDS Device D LDTACK DSr LDS VME Bus Controller DSw LDTACK D DTACK DTACK Read Cycle VME bus

  14. STG for the READ cycle DSr+ DTACK- LDS+ LDTACK+ D+ DTACK+ DSr- D- LDTACK- LDS- D LDS DSr VME Bus Controller LDTACK DTACK

  15. DSr+ DSw+ LDS+ D+ LDTACK+ LDS+ LDTACK- DTACK- DTACK- LDTACK- D+ LDTACK+ DTACK+ D- LDS- LDS- DSr- DTACK+ D- DSw- Choice: Read and Write cycles

  16. DSr+ DSw+ LDS+ D+ LDTACK+ LDS+ LDTACK- DTACK- DTACK- LDTACK- D+ LDTACK+ DTACK+ D- LDS- LDS- DSr- DTACK+ D- DSw- Choice: Read and Write cycles

  17. Circuitsynthesis • Goal: • Derive a hazard-free circuitunder a given delay model andmode of operation

  18. Modes of operation • Fundamental mode • Single-input changes • Multiple-input changes • Input / Output mode • Concurrencycircuit / environment Currentstate Nextstate

  19. STG for the READ cycle DSr+ DTACK- LDS+ LDTACK+ D+ DTACK+ DSr- D- LDTACK- LDS- D LDS DSr VME Bus Controller LDTACK DTACK

  20. Speed independence • Delay model • Unbounded gate / environment delays • Certain wire delays shorter than certain paths in the circuit • Conditions for implementability: • Consistency • Complete State Coding • Output persistency

  21. Other synthesis approaches • Burst-mode machines • Mealy-like FSMs • Fundamental mode (slow environment) • VLSI programming • Syntax-directed translation from CSP(“Communicating Sequential Processes”) • No logic synthesis • Circuit size ~ Size of the specification

  22. Specification(STG) Reachability analysis State Graph State encoding SG withCSC Design flow Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist

  23. State Graph (Read cycle) DSr+ DTACK- LDS+ LDTACK- LDTACK- LDTACK- DSr+ DTACK- LDS- LDS- LDS- LDTACK+ DSr+ DTACK- D+ D- DTACK+ DSr-

  24. LDS + LDS = 0 LDS - LDS = 1 Binary encoding of signals DSr+ DTACK- LDS+ LDTACK- LDTACK- LDTACK- DSr+ DTACK- LDS- LDS- LDS- LDTACK+ DSr+ DTACK- D+ D- DTACK+ DSr-

  25. 01100 00110 Binary encoding of signals 10000 DSr+ DTACK- LDS+ LDTACK- LDTACK- LDTACK- DSr+ DTACK- 10010 LDS- LDS- LDS- LDTACK+ DSr+ DTACK- 10110 01110 10110 D+ D- DTACK+ DSr- (DSr , DTACK , LDTACK , LDS , D)

  26. ER (LDS+) LDS+ QR (LDS-) LDS- LDS- LDS- ER (LDS-) QR (LDS+) Excitation / Quiescent Regions

  27. LDS+ LDS- LDS- LDS- 10110 10110 Next-state function 0  1 0  0 1  1 1  0

  28. DTACK DSr DTACK DSr D LDTACK D LDTACK 00 00 01 01 11 11 10 10 00 00 01 01 11 11 10 10 Karnaugh map for LDS LDS = 1 LDS = 0 - - - 0 0 - 1 1 - - - - - - - - 1 1 1 - - - - - 0 0 - 0 0 0 - 0/1?

  29. Specification(STG) Reachability analysis State Graph State encoding SG withCSC Design flow Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist

  30. DSr+ DSr+ DSr+ Concurrency reduction LDS+ LDS- LDS- LDS- 10110 10110

  31. Concurrency reduction DSr+ DTACK- LDS+ LDTACK+ D+ DTACK+ DSr- D- LDTACK- LDS- (See today’s presentation in this workshop for more details)

  32. State encoding conflicts LDS+ LDTACK- LDS- LDTACK+ 10110 10110

  33. CSC+ CSC- Signal Insertion LDS+ LDTACK- LDS- LDTACK+ 101101 101100 D- DSr-

  34. Specification(STG) Reachability analysis State Graph State encoding SG withCSC Design flow Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist

  35. Complex-gate implementation

  36. Specification(STG) Reachability analysis State Graph State encoding SG withCSC Design flow Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist

  37. abcx 1000 b+ 0 1 0 1 a 1100 1 x 0 1 1 0 b a- 0 c 1 0 0 0100 c+ 0110 Hazards

  38. abcx 1000 b+ 0 1 0 1 0 0 0 1 a 0 0 1 1 0 0 1 1 z 1100 1 1 b x 1 1 1 0 1 1 1 0 0 0 0 0 0 1 c a- 0 0 1 1 0 1 0 1 0100 c+ 0110 Hazards 1000 1100 1100 0100 0110

  39. Decomposition • Global acknowledgement • Generating candidates • Hazard-free signal insertion • Event insertion • Signal insertion

  40. d- b+ d+ y+ a- y- c+ d- c- d+ z- b- z+ c+ a+ c- c z b a a y b d Global acknowledgement

  41. d- b+ d+ y+ a- y- c+ d- c- d+ z- b- z+ c+ a+ c- c z b a a y b d How about 2-input gates ?

  42. d- b+ d+ y+ a- y- c+ d- c- d+ z- b- z+ c+ a+ c- How about 2-input gates ? c z b a a y b d

  43. d- b+ d+ y+ a- y- c+ d- c- d+ z- b- z+ c+ a+ c- How about 2-input gates ? 0 c 0 z b a a y b d

  44. d- b+ d+ y+ a- y- c+ d- c- d+ z- b- z+ c+ a+ c- How about 2-input gates ? c z b a a y b d

  45. d- b+ d+ y+ a- y- c+ d- c- d+ z- b- z+ c+ a+ c- a b How about 2-input gates ? c z y d

  46. Strategy for correct logic decomposition • Each decomposition defines a new internal signal of the circuit • Method: Insert new internal signals such that • After resynthesis,some large gates are decomposed • The new specification is hazard-free under unbounded gate delays

  47. y- y- 1001 1011 z- w- 1000 0001 w+ y+ w- z- x+ z- w- w+ 1010 0000 0101 0011 w- y+ x+ z- y+ x+ x- 0010 0100 x- x+ y+ z+ 0110 0111 z+ Decomposition example

  48. x y- y- y w 1001 1001 1011 1011 z z- z- w- w- y 1000 1000 0001 0001 w+ w+ z y+ y+ x w- w- z- z- x+ x+ w 1010 1010 0000 0000 0101 0101 0011 0011 w w- w- y+ y+ x+ x+ z- z- C z y z 0010 0010 0100 0100 x- x- x+ x+ y+ y+ y z+ z+ C 0110 0110 0111 0111 x z y yz=0 yz=1

  49. x s=1 w y 1001 1011 z- s- z w+ 1001 1000 z- x s- y+ w- w 0011 1000 0001 1010 w y+ s- w- z- x+ x- C z y 1010 0000 0101 z w- y+ x+ z- 0111 y 0010 0100 C x z s+ x+ y+ s=0 z+ y 0111 0110 y- s

  50. y- 1001 1011 z- s- s- s- s- s- s- s- s- w+ 1001 1000 z- y+ w- 0011 1000 0001 z- w- w+ 1010 y+ w- z- x+ x- 1010 0000 0101 w- y+ x+ z- y+ x+ x- 0111 0010 0100 x+ y+ s+ s+ s+ s+ s+ s+ s+ s+ z+ z+ 0111 0110 s=1 y- s- s- s- s+ s=0

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