Programmable and Adaptive Analog Floating-Gate Circuits

1. Programmable and Adaptive Analog Floating-Gate Circuits Jeff Dugger Georgia Tech School of ECE 2001 Telluride Neuromorphic Workshop

2. Overview of Floating-Gate Systems • Basic Floating-Gate Operation: • Computation • Weight Storage • Weight Programming and Adaptation Mechanisms • Computing in Memory: • programmable/adaptive vector-matrix core • Programming infrastructure and methods • Adaptation via correlation learning rules

3. Subthreshold MOSFET Subthreshold Current-Voltage Relation Current is exponentially related to gate voltage

4. Linearized Model

5. Computation: Transconductance Amplifier Linearized Model

6. + Transconductance Amplifier Basic Floating-Gate Transistor: Storage & Computation Capacitive Divider

7. Capacitor-coupled transconductance Weight Basic Floating-Gate Transistor:Storage & Computation

8. Floating-Gate 4 Quadrant Multiplication V V 23 dd dd 22 V V nA) tun tun 21 V dibl 20 Output Current ( + - W = 0 W = 0 V V in in 19 W = -0.35 W = 0.35 W = -0.70 W = 0.70 18 + - I I out out W = -1.40 17 W = 1.40 I out -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 Differential input (V)

9. Iout1 W24 W12 W13 W14 W15 W1n W21 W23 W22 W25 Wm1 Wm2 Wm3 Wm4 Wm5 Wmn W11 W2n Iout2 Iout_m Vector-Matrix Array n Columns m Rows

10. Vin Bandpass Filters, Exp Spaced (Hard in DSP) Bandpass Filters W11 W12 W13 W14 W15 W21 W23 W24 W25 W2n W1n W22 Iout1 Iout2 Programmable Analog Filter Analogous to FFT / IFFT DSP based filters Vector-Matrix Analog Signal Processing

11. Tunneling Current • Injection Current Basic Floating-Gate Transistor:Weight Change Mechanisms pFET Floating-Gate Synapse Change floating-gate charge using:

12. Electron Tunneling (oxide voltage)-1 Increasing the applied voltage decreases the effective barrier width The range of tunneling currents span many orders of magnitude.

13. Vinj = 430mV pFET Hot-Electron Injection The injected electrons are generated by hole impact ionizations. **Injection current is proportional to source current, and is an exponential function of Fdc.

14. wi weight storage... xi wi multiplication... dwi / dt = f(wi) and adaptation In the space of about 1 0 1 0 4 bits of EEPROM memory Computing in Memory Analog Floating-Gate pFET synapses provide Very Dense!

15. Gate voltage required to create a channel for current to flow • Large Source to drain voltage required for high field to make electron hot Programming a FG Injection- 2 conditions must be met for injection

16. Basic Programming Structure • Injection • Requires Voltage across the • Source-Drain • Requires Voltage on the Gate • Tunneling • Requires a voltage across the • tunneling cap.

17. Basic Programming Structure Injection • Gate: Column isolation • Both: Device isolation • Source-Drain: Row isolation

18. Programming a FG Tunneling- • Voltage across the tunneling capacitor determines if tunneling occurs. • Voltage on gate will change this voltage.

19. HV Decoding Basic Programming Structure Tunneling • Column isolated • Device isolated Require HV switches More area required

20. Selectivity in Array

21. Basic Programming Structure

22. Programming Board, v0.1

23. Autozeroing Floating-Gate Amplifier (AFGA)

24. Amplitude Effects in the AFGA This wouldn’t happen in a linear system Continuous-time correlations

25. Tunneling Current • Injection Current From KCL at floating-gate: Single Transistor Floating-Gate Synapse: Adaptation pFET Floating-Gate Synapse Adapts floating-gate charge using:

26. Weight Dynamics

27. Correlation Learning Rule

28. Gate-Drain Weight Correlation 2 Inputs: Vg = V1 sin wt Vd = V2 sin wt 1. 9 Weq - E[ Vd Vg ] = - V1 V2 1. 8 Vg = 1.72V 1. 7 Fix V1 (three amplitudes) 1. 6 Equilibrium Weight Vg = 1.29V 1. 5 Sweep V2 1. 4 1. 3 Vg amplitude = 0. 86 V 1. 2 1. 1 1 -0 .2 0 -0 .1 6 -0 .1 2 -0 .0 8 -0 .0 4 0 0. 0 4 0. 0 8 0. 1 2 0. 1 6 0. 2 0 Drain voltage amplitud e (V)

29. Gate-Drain Weight Correlation 1.7 Inputs: Vg = V1 sin wt Vd = V2 sin(wt + q) 1.65 1.6 Vd ampl itude = 0.1896V 1.55 1.5 Sweep q Weight 1.45 Vd ampl itude = 0.1264V 1.4 Fix V1, V2 (two V2 amplitudes) 1.35 Weq - E[ Vd Vg ] = - V1 V2 cos(q) 1.3 1.25 1.2 0 50 10 0 15 0 20 0 25 0 30 0 35 0 Phase dif ference return

30. Differential Synapse

31. Large Offset 2. Continuously adapt one pFET device, and program the other device Distortion Differential Synapse Two cases: 1. Continuously adapt Both pFET devices

32. _ + Quad Differential Synapse

33. Quad Differential Synapse input signal learning signal output signal Equilibrium Weight:

34. Floating-Gate Transistor Node

35. 4 3 2 1 0 - 1 0 10 20 30 40 50 60 I bias = 5.4mA, I bias = 3.7mA 1 2 Synapse Weight Convergence sin(wt) sin(3wt) learning signal output signal I 100nA) 2 3.4s I 1 ents ( e Curr sin(0.7wt) Synaps sin(wt) sin(3wt) sin(wt) Time (s) t = 6.5s [Dugger and Hasler, 2000]

36. 3 2 1 Output Current (mA) 0 -1 -2 0 10 20 30 40 50 60 70 80 90 Tim e ( ms) Learning a Square Wave sin(wt) sin(3wt) square(wt) output signal

37. Vd = f(Iy,Vtarget) Vtarget Learning Rule Circuits

38. Adaptive Diff-Pair