Latches and Flip-Flops

Latches and Flip-Flops Discussion D6.1

Latches and Flip-Flops • Latches • SR Latch • D Latch • Flip-Flops • D Flip-Flop • JK Flip-Flop • T Flip-Flop

Sequential Logic • Combinational Logic • Output depends only on current input • Sequential Logic • Output depends not only on current input but also on past input values • Need some type of memory to remember the past input values

Cross-coupled Inverters State 1 State 2

SR Latch S' R' Q Q' 1 0 0 0 0 1 1 0 1 1 1 1 0 1 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

SR Latch S' R' Q Q' 0 1 0 0 0 1 1 0 1 1 1 0 Set 0 1 0 1 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

SR Latch S' R' Q Q' 1 1 0 0 0 1 1 0 1 1 1 0 Set 0 1 0 1 Store 1 0 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

SR Latch S' R' Q Q' 1 0 0 0 0 1 1 0 1 1 1 0 Set 0 1 Reset 1 0 0 1 Store 1 0 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

SR Latch S' R' Q Q' 1 0 0 0 0 1 1 0 1 1 1 0 Set 0 1 Reset 1 1 0 1 Store 1 0 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

SR Latch S' R' Q Q' 0 1 0 0 0 1 1 0 1 1 1 1 Disallowed 1 0 Set 0 1 Reset 1 0 0 1 Store 1 0 Q0 Q0' X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

SR Latch S' R' Q Q' 1 0 0 0 0 1 1 0 1 1 1 1 Disallowed 1 0 Set 0 1 Reset 1 1 0 1 Store 1 0 Q0 Q0' X Y nand 0 0 1 0 1 1 1 0 1 1 1 0 To close or lock with or as if with a latch, To catch or fasten

S EN R S R EN S' R' Q Q' SR Latch with Enable S' Q Q' R' 0 0 1 1 1 Q0 Q0' Store 0 1 1 1 0 0 1 Reset 1 0 1 0 1 1 0 Set 1 1 1 0 0 1 1 Disallowed X X 0 1 1 Q0 Q0' Store

RS Latch R Q S RS Latch Q is set to 1 when S is asserted, and remains unchanged when S is disasserted. Q is reset to 0 when R is asserted, and remains unchanged when R is disasserted. Assertions can be active HIGH or active LOW

RS Latch R Q S library IEEE; use IEEE.STD_LOGIC_1164.all; entity rslatch is port( R : in STD_LOGIC; S : in STD_LOGIC; Q : out STD_LOGIC ); end rslatch; architecture rslatch of rslatch is begin process(R,S) begin if S = '1' and R = '0' then Q <= '1'; elsif S = '0' and R = '1' then Q <= '0'; end if; end process; end rslatch; Active HIGH

RS Latch -- Active High

RS Latch R Q S library IEEE; use IEEE.STD_LOGIC_1164.all; entity rslatch is port( R : in STD_LOGIC; S : in STD_LOGIC; Q : out STD_LOGIC ); end rslatch; architecture rslatch of rslatch is begin process(R,S) begin if S = '0' and R = '1' then Q <= '1'; elsif S = '1' and R = '0' then Q <= '0'; end if; end process; end rslatch; Active LOW

RS Latch -- Active Low

RS Latch R Q S How can you make this RS latch from gates? Q is set to 1 when S is asserted, and remains unchanged when S is disasserted. Q is reset to 0 when R is asserted, and remains unchanged when R is disasserted. Assertions can be active HIGH or active LOW

SQ RS Latch 00 01 11 10 R R Q 0 S 1 Q is set to 1 when S is asserted (1), and remains unchanged when S is disasserted (0). Q is reset to 0 when R is asserted (1), and remains unchanged when R is disasserted (0). R S Q Q 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 store 1 1 1 set 1 reset store Q = R'Q + R'S + SQ

RS Latch R Q S RS Latch R S Q Q 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 store set reset store Q = R'Q + R'S + SQ

library IEEE; use IEEE.STD_LOGIC_1164.all; entity rslatchgates is port( R : in STD_LOGIC; S : in STD_LOGIC; Q : out STD_LOGIC ); end rslatchgates; architecture rslatchgates of rslatchgates is signal Q1: std_logic; begin Q1 <= (not R and Q1) or (not R and S) or (S and Q1); Q <= Q1; end rslatchgates; Q1

D Latch D Q EN D Latch Q follows D when EN is high, and remains unchanged when EN is low..

D Latch D Q EN library IEEE; use IEEE.STD_LOGIC_1164.all; entity dlatch is port( D : in STD_LOGIC; EN : in STD_LOGIC; Q : out STD_LOGIC ); end dlatch; architecture dlatch of dlatch is begin process(D,EN) begin if EN = '1' then Q <= D; end if; end process; end dlatch;

D Latch

D S R EN Q Q' D EN Q Q' 0 0 1 Q0 Q0' Store 0 1 1 0 1 Reset 1 0 1 1 0 Set 1 1 1 1 1 Disallowed X X 0 Q0 Q0' Store 0 1 0 1 1 1 1 0 X 0 Q0 Q0' D Latch S S' Q EN Q' R' R

D D EN Q Q' 0 1 0 1 1 1 1 0 X 0 Q0 Q0' D Latch S S' Q EN Q' R' R Note that Q follows D when EN in high, and is latched when EN goes to zero.

Q D clk Q' D clk Q Q' 0 0 1 1 1 0 X 0 Q0 Q0' D Flip-Flop Positive edge triggered D gets latched to Q on the rising edge of the clock. Behavior if rising_edge(clk) then Q <= D; end if;

Q D clk Q' library IEEE; use IEEE.STD_LOGIC_1164.all; entity dflipflop is port( D : in STD_LOGIC; clk : in STD_LOGIC; Q : out STD_LOGIC; NotQ : out STD_LOGIC ); end dflipflop; architecture dflipflop of dflipflop is signal QS: STD_LOGIC; begin process(D,clk) begin if rising_edge(clk) then QS <= D; end if; end process; Q <= QS; NotQ <= not QS; end dflipflop;

D Flip-Flop

Q D clk Q' library IEEE; use IEEE.STD_LOGIC_1164.all; entity dflipflop is port( D : in STD_LOGIC; clk : in STD_LOGIC; Q : out STD_LOGIC; NotQ : out STD_LOGIC ); end dflipflop; architecture dflipflop of dflipflop is signal QS: STD_LOGIC; begin process(D,clk) begin if clk'event and clk = '1' then QS <= D; end if; end process; Q <= QS; NotQ <= not QS; end dflipflop;

D Flip-Flop

Master-Slave D Flip-Flop

Recall the SR Latch S' R' Q Q' 0 1 0 0 0 1 1 0 1 1 1 1 Disallowed 1 0 Set 0 1 Reset 1 0 0 1 Store 1 0 Q0 Q0' X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

Edge-triggered D Flip-flop 1 1 0 1 1 0

Edge-triggered D Flip-flop 1 1 0 1 1 0 1 0

Latches and Flip-Flops