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ECE122 – Lab 5 Latches & Flip-flops

The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering. ECE122 – Lab 5 Latches & Flip-flops. Jason Woytowich Ritu Bajpai Last revised on October 15, 2007. What are Latches & Flip-flops?.

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ECE122 – Lab 5 Latches & Flip-flops

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  1. The George Washington UniversitySchool of Engineering and Applied ScienceDepartment of Electrical and Computer Engineering ECE122 – Lab 5 Latches & Flip-flops Jason Woytowich Ritu Bajpai Last revised on October 15, 2007

  2. What are Latches & Flip-flops? • They are single bit memory elements • Latches change state whenever the inputs dictate it • Flip-flops only change state on rising or falling clock edges

  3. Lab Activities • Build and test an SR Latch from NAND Gates. • Build and test a D Latch from the SR Latch • Build and test a DFF from your D Latch: • Master Slave implementation (MS) • Positive gate trigger implementation (PGT) • We will do only schematic simulation in today's lab and will test our circuit for all possible combinations of input.

  4. Truth table for SR Latch • Set/Reset Latch

  5. Schematic design for SR Latch • NAND Implementation

  6. Can you make a schematic design for a SR NOR latch? • Start from NAND latch. • Show step by step procedure to replace NAND gates by NOR gates. • Do the inputs/outputs remain the same for NAND and NOR latch?

  7. Output waveform for SR Latch(NAND implementation)

  8. Truth table for D Latch • A Gated Latch

  9. Schematic design for a D Latch • An SR Latch implementation

  10. Output waveform for a D Latch

  11. D Flip-Flop (DFF) • The value of D is stored on either the rising or falling clock edge. • The figure below shows the positive edge triggered D flip flop. Clock D Q

  12. Schematic design for a DFF • Master-Slave Implementation

  13. Output waveform for a DFF

  14. DFF • Gate Trigger Implementation

  15. Schematic for a Positive Gate Trigger There are an odd number of inverters.

  16. Output waveform for a Positive Gate Trigger (PGT)

  17. Can you explain the output waveform of the PGT? • Why do we use an odd number of inverters to make a PGT? • Could we have used even number of inverters and replaced the AND gate by NOR, NAND or OR gate to obtain a similar output?

  18. Output waveform for a DFF

  19. Results • Give clear output waveforms for all the circuits that you implemented in today’s lab. • Ensure that our output waveforms show that you have covered all the test cases.

  20. Analysis • So far you have seen that you obtain glitches or peaks in your output during transition of input from one state to another. After doing this lab can you suggest a way to get rid of those glitches and peaks? • Keeping the above question in mind can you state one probable use of D flip flops in digital circuits?

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