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Assessing Chip-Level Impact of Double Patterning Lithography

Assessing Chip-Level Impact of Double Patterning Lithography. Kwangok Jeong * , Andrew B. Kahng *,** , and Rasit O. Topaloglu *** http://vlsicad.ucsd.edu/ * ECE Dept., UC San Diego ** CSE Dept., UC San Diego *** GlobalFoundries, Inc. Outline. Double Patterning Lithography (DPL)

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Assessing Chip-Level Impact of Double Patterning Lithography

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  1. Assessing Chip-Level Impact of Double Patterning Lithography Kwangok Jeong*, Andrew B. Kahng*,**, and Rasit O. Topaloglu*** http://vlsicad.ucsd.edu/ * ECE Dept., UC San Diego ** CSE Dept., UC San Diego *** GlobalFoundries, Inc.

  2. Outline • Double Patterning Lithography (DPL) • Traditional Interconnect Analysis • Additional Variability in DPL • Misalignment in Double Patterning • Analysis in Different DPL Options • Experiments • Conclusion

  3. Outline • Double Patterning Lithography (DPL) • Traditional Interconnect Analysis • Additional Variability in DPL • Misalignment in Double Patterning • Analysis in Different DPL Options • Experiments • Conclusion

  4. Double Patterning Lithography (DPL) • Pattern-doubling: • ‘2X-resolution’ lithography with ‘1X-resolution’ equipment • Taxonomy • Resist type: positive /negative • Methods: double exposure (DE) / double patterning (DP) / spacer double patterning (SDP) • Printed feature: line / space Resist Target layer Mask1 Resist 1X 1st Exposure Target layer Mask Mask2 1X 2nd Exposure 1X-resolution 2X-resolution

  5. Traditional Interconnect Analysis • Designers use capacitance tables from foundries • 2D/3D field solver with variations  Capacitance tables • Major sources of variation: • Metal/dielectric density-dependent systematic variation • Random process variation • Results of variation • Width (W) variation • Metal height (H) variation • Dielectric thickness (D) variation, etc. • Traditional interconnect variation analysis M+1 • 1. for (i = -3 ; i  3 ; i=i+1) { • for (j = -3 ; j  3 ; j=j+1) { • for (k = -3 ; k  3 ; k=k+1) { • W=Wnom + iW • H= Hnom + jH • D= Dnom + kD • run field solver over • parameterized structure}}} • Find nominal and worst-case capacitance H M W D M-1

  6. Additional Variability in DPL • Overlay error • Causes: • mask misalignment • material stress-impacted deformations • litho-/etch-impacted topography • lens aberration, etc. • Impacts on DPL • Width variation • Space (or pitch) variation  Capacitance variation • Alignment metric • Indirect: • Two DPL masks aligned to a reference layer • Error: • Direct: • Second DPL mask aligned to the first DPL mask • Error: Direct Alignment (DA) Indirect Alignment (IA) S S S S Cc Cg

  7. Outline • Double Patterning Lithography (DPL) • Traditional Interconnect Analysis • Additional Variability in DPL • Misalignment in Double Patterning • Analysis in Different DPL Options • Experiments • Conclusion

  8. S Misalignment in Positive DE/DP mask1 (misaligned to left) mask2 Positive photoresist Dielectric After exposure + etch Cu filling Space on one side increases Space on the other side decreases Required design of experiments foreach S (-3 ~ 3) mask1  shift by +S/2 mask2  shift by –S/2 end S 1 2 1 2 1 W W

  9. S S Misalignment in Negative DE/DP mask1 mask2 (misaligned to left) Negative photoresist Dielectric After exposure + etch After filling Cu Width of one increases Width of the other decreases Required design of experiments foreach S  (-3 ~ 3) mask1  change Wby +S  shift by S/2 mask2  change W by –S  shift by S/2 end 1 2 1 2 1 W’’ W’ P P S/2

  10. S S Spacer Thickness Variation in Positive SDP Primary patterns Spacers (act as if masks) (kind of) Positive photoresist Dielectric After exposure + etch After filling Cu Cu 1 2 1 2 1 Width and space change Required design of experiments foreach S  (-3 ~ 3) mask1  change W by 0 mask2  change W by +S end W’’ W P P

  11. S S Spacer Thickness Variation in Negative SDP Primary patterns Spacers (act as if masks) (kind of ) Negative photoresist Dielectric After exposure + etch After filling Cu Cu Width and space change Required design of experiments foreach S  (-3 ~ 3) mask1  change W by +S/2  shift by +S/4 mask2  change W by +S/2  shift by –S/4 end 1 2 1 2 1 W’ W’ P’’ P’

  12. Outline • Double Patterning Lithography (DPL) • Traditional Interconnect Analysis • Misalignment in Double Patterning • Analysis in Different DPL Options • Experiments • Conclusion

  13. Experiments: Scenarios • We examine impact of misalignment and linewidth variation across various DPL options Alignment Photoresist Process DE Parallel 5-Interconnect Structure (TCAD tool) Positive Indirect Positive DP Negative Negative Direct SDP DE Direct Interconnects in a full-chip (Signoff RCX) DP SDP

  14. TCAD-Based BEOL Analysis Results • Capacitance variation due to misalignment in DE/DP • IA shows larger variation than DA • Negative resist processes have larger variation • Capacitance variation in different DPL options • SDP has larger variation • Negative resist processes have larger variation Capacitance (aF/um) Capacitance (aF/um)

  15. Design-Level Analysis - Flow • Overlay-aware extraction flow TOP.GDS AES core with NanGate 45nm Tech. 1. Design GDS Initial GDS 2. Split GDS ILP-based min cost coloring (Kahng et al. ICCAD08) Non-DPL layers 3. Pattern Decomposition DPL layers Sub-GDS1 Base GDS Coloring and Splitting Sub-GDS1-1 Sub-GDS2 Sub-GDS1-2 Sub-GDS2-1 4. Shift and Merge (Cadence Virtuoso) Sub-GDS2-2 Shifting and Merging TOP.GDS 5. Resize and Extraction (Synopsys Hercules, Star-RCXT) Resizing

  16. Design-Level Capacitance Variation • Overlay error can cause more than +/- 10% capacitance variation within a die, for all DPL options  Large on-chip variation  Increase of timing optimization difficulty Capacitance Variation (%) M4 M5 M3 M2

  17. Maximum Crosstalk-Induced Delay • A net having maximum crosstalk delay (17um long) • SDP shows more sensitivity  tighten overlay spec • P-DE/DP shows least sensitivity  lessen overlay spec M4 M4 M2 M2 M4 |S| |S|/2 |S|/2 |S|/2 P-DE/DP (Space on one side) N-DE/DP (Width) P-SDP (Spaces on both sides) N-SDP (Space & width) w/o metal fill w/ metal fill

  18. Total Negative Slack Variation • SDP, especially for lower layer (smaller feature), shows more sensitivity  tighter overlay spec TNS Variation (%)

  19. Outline • Double Patterning Lithography (DPL) • Traditional Interconnect Analysis • Misalignment in Double Patterning • Analysis in Different DPL Options • Experiments • Conclusion

  20. Summary of Observations • Overlay error with indirect alignment (IA) results in higher capacitance variations compared to direct alignment (DA) • Capacitance can vary > 10% due to misalignment  Large OCV  increase timing optimization difficulty • Timing can be degraded significantly, e.g., > 10% worse TNS • P-DE/DP may be the most favorable option for BEOL DPL • With the same 3 overlay control, the variation in P-DE/DP is 50% of N-DE/DP or P-SDP, and 25% of N-SDP   Overlay control spec for P-DE/DP can be relaxed by 2X compared to others

  21. Conclusion and Ongoing Work • We provide a variational interconnect analysis framework for double patterning lithography • We analyze mechanisms of interconnect variations due to misalignment and spacer thickness variation in DPL • We provide both interconnect and design-level RC-extraction framework reflecting interconnect variation in a 45nm DPL process • We compare the impact of overlay error in different DPL options • Ongoing work • Development of timing analysis and optimization methodology considering interconnect variation in DPL • Incorporation of statistical techniques to target pessimism reduction

  22. Thank You!

  23. Impact of Misalignment on FEOL • Standard cell decomposition • Experimental setup • 10nm 3 misalignment is assumed between layers • Design of experiments (all permutation: 3*3*3*3 = 81 cases) • P1: -10nm (L) / 0nm (C) / +10nm (R) • P2: -10nm (L) / 0nm (C) / +10nm (R) • M: -10nm (L) / 0nm (C) / +10nm (R) • C: -10nm (L) / 0nm (C) / +0nm (R) Original P1 P2 M C BASE

  24. Experimental Results on FEOL • Flow • Impact of misalignment on cell delay is negligibly small (< 2%) • Capacitance variation due to misalignment << gate capacitance • Measured Delay Variation (%) Tr-level RC-Extraction STAR-RCXT Circuit Simulation HSPICE

  25. DPL Options • Spacer-DP • Double Exposure • Double Patterning Mask Resist Resist Resist Hardmask Hardmask Target layer Buffer oxide Target layer Hardmask Target layer Mask1 Mask1 Target layer 1st Litho-etch mask 1st Exposure 1st Litho-etch positive resist Mask2 negative resist Mask2 Spacer formation Oxide depo. CMP 2nd Litho-etch 2nd Exposure Dielectric After exposure & etch 2nd etch Cu interconnect Spacer removal • Printed Feature • Photoresist After Cu filling mask (a) Positive-tone (b) Negative-tone positive resist Dielectric Poly After exposure & etch Cu interconnect Poly (a) Spaces (Trench-First) (b) Lines

  26. Mask Coloring and Layout Examples in DPL • Mechanism of misalignment-induced variation 2 2 4 4 2 4 4 2 S S 6 6 6 6 1 1 1 1 3 5 3 3 5 5 3 5 Original patterns Coloring Patterns 1 Patterns 2 (a) DE and DP Process Dummy for pattern 6 Spacer (gray) a Narrow space b 2 4 W 1 6 3 5 W” Original patterns Coloring Trim & repair (dark gray) Spacer formation (Large spacer) (b) SDP Process

  27. Design-Level Analysis - DOE • Design of Experiments for DE/DP with DA • foreachlayer { M2, M3, M4, M5 } • decompose layer into layermask1 and layermask2 • foreachS { -3/2, -2/2, -/2, 0, /2, 2/2, 3/2} • shift layermask1 by S • shift layermask2 by –S • end • layer layermask1 + layermask2 • foreachW { -3/2, -2/2, -/2, 0, /2, 2/2, 3/2} • resize layer by W • end • merge with other layers • RC-Extraction and Timing Analysis • end

  28. Impact on Capacitance Variation • Total interconnect capacitance: maximum C(%) • Among top 20% high capacitance nets • Impact of overlay < impact of width • Sum of capacitance in the most critical path • Critical path has short interconnects  impact of BEOL variation significantly reduces • Impact of overlay < impact of width

  29. Impact on Crosstalk-Induced Delay • Maximum coupling induced delay change • PrimeTime-SI (Synopsys) is used to find a net that is mostly affected due to crosstalk • Temporal/functional filtering is performed • Selected net structure • A net with relatively small length (~17um) can have >10% delay changes due to overlay error M4 segment: 14.788um M2 segment: 1.604um M3 segment: 0.78um Capacitance when Delay is maximum Capacitance when Delay is minimum

  30. Impact on Timing • Longest path and total negative slack (TNS) • Impact of overlay << impact of width • Longest path delay changes negligibly • However, overall timing (TNS) can change significantly Total Negative Slack (ns)

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