Double Patterning Lithography-Aware Analog Placement

1. Double Patterning Lithography-Aware Analog Placement Hsing-Chih Chang Chien Hung-ChihOu Tung-Chieh Chen Ta-Yu Kuan Yao-Wen Chang

2. Outline • Introduction • DPL conflict handling • The algorithm flow • Experimental results • Conclusions

3. Introduction • DPL • decompose patterns of a layer into two sub-patterns and then use two masks to manufacture the two sub-patterns

4. DPL conflict • Two patterns separated by the distance less than Sminbelong to the same mask.

5. Analog Placement Problem • Previous Works • corner stitching compliant B*-tree (CB-tree) [14] • DPL is not considered in previous works.

6. Analog designers usually reduce mismatches by predefining masks (colors)

7. Preliminaries • For constraint-driven analog placement, CB-tree is the most effective and efficient topological representation with module adjacency information

8. Review of Corner Stitching • Corner stitching is a data structure for representing non-overlappingrectangular modules in a two-dimensional plane (called tile plane).

10. Analog Constraints • Symmetry constraints • are use to place some pairs of modulessymmetrically along a vertical or a horizontal symmetry axis.Itcan reduce mismatches of sensitive modules. • Proximity constraints • are use to place modules at closest proximityto reduce process variation.

11. Problem Formulation • Rectangular modules M = {mk|1 ≤ k ≤ |M|} • Nets N = {nk|1 ≤ k ≤ |N|} • Placement Constraints S = {sk|1 ≤ k ≤ |S|} • Pre-coloring Constraints R = {rk|1 ≤ k ≤ |R|} • Place all modules in M to minimize the total area, wirelength, and DPL conflict

12. DPL conflict handling • Resolving an analogplacement with DPL conflicts. • extended conflict graph(ECG) to model the global relationshipamong patterns/modules.

13. Module Flipping

14. Extended Conflict Graph (ECG) • The traditional conflict graphconsiders the information from a fixed layout. • Since a poly can only be placed vertically, there are only two choices for module orientations: non-flipped and flipped.

17. Basic Integer Linear Programming (ILP) Formulation

19. ILP Problem-Size Reduction • Connected Component Computation • Two-Edge-Connected Component Computation • identify a bridge

20. The algorithm flow

21. Perturbation • In stage 1 & 3 • In stage 2

23. The Three-Stage Placement Flow

24. Tile Plane Updating • to create new tiles and update the corner stitches to record the neighbors for each tile.

26. Experimental results • C++programming language. • Intel Xeon X5647 2.93GHz Linux workstation with48GB memory. • CPLEX12.3 [1] library to solve the ILP problems. • Two industrial analog circuits Case1 and Case2.

29. Conclusions • DPL-aware analog placement flow to simultaneously minimize area, wirelength, and DPL conflicts. • Propose an extended conflict graph (ECG). • Develop anILP algorithm consideringsymmetry and pre-coloring constraints to minimize conflicts. • A three-stage flow.