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Revisiting the Layout Decomposition Problem for Double Patterning Lithography

Revisiting the Layout Decomposition Problem for Double Patterning Lithography. Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Yao http://vlsicad.ucsd.edu/ University of California, San Diego. Outline. Background Contributions DPL Layout Decomposition Flow

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Revisiting the Layout Decomposition Problem for Double Patterning Lithography

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  1. Revisiting the Layout Decomposition Problem for Double Patterning Lithography Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Yao http://vlsicad.ucsd.edu/ University of California, San Diego UCSD VLSI CAD Laboratory BACUS-2008

  2. Outline • Background • Contributions • DPL Layout Decomposition Flow • DPL Color Assignment Problem Formulation • Experimental Results • Summary UCSD VLSI CAD Laboratory BACUS-2008

  3. Background: DPL DPL is a primary lithography candidate for 32nm node Partitions dense circuit patterns into two separate exposures Improves resolution and depth of focus (DOF) Two primary approaches LELE (litho-etch-litho-etch) Self-aligned Major concern is overlay control Requires more accurate overlay metrology, more representative sampling, reduced model residuals, and improved overlay correction ITRS DPL overlay control requirement is 6-9nm  challenging for production deployment UCSD VLSI CAD Laboratory BACUS-2008

  4. Background: Layout Decomposition Two features are assigned opposite colors if their spacing is less than the minimum coloring spacing IF two features within minimum coloring spacing cannot be assigned different colors THEN at least one feature is split into two or more parts Pattern split increases manufacturing cost, complexity Line ends  corner rounding Overlay error and interference mismatch  line edge errors  tight overlay control Optimization : minimize cost of layout decomposition UCSD VLSI CAD Laboratory BACUS-2008

  5. Outline • Background • Contributions • DPL Layout Decomposition Flow • DPL Color Assignment Problem Formulation • Experimental Results • Summary UCSD VLSI CAD Laboratory BACUS-2008

  6. Contributions Reference [1] (our group, Proc. ICCAD-2008) Integer linear programming (ILP) Conflict cycle detection and removal Report unresolvable conflict cycles This work Consider all feasible splitting points for layout features Different ILP formulation  minimize design changes, line-ends; maximize overlap length Phase conflict detection (PCD) method [2]  good solution quality, much less runtime Node-deletion bipartization (NDB) method [3]  also fast, worse solution quality Report deleted conflict edges  more direct metric of design changes [1] A. B. Kahng, C.-H. Park, X. Xu and H. Yao, “Layout Decomposition for Double Patterning Lithography”, Proc. IEEE Intl. Conf. on Computer-Aided Design, 2008. [2] C. Chiang, A. B. Kahng, S. Sinha, X. Xu, and A. Zelikovsky, "Fast and Efficient Bright-Field AAPSM Conflict Detection and Correction", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 26(1) (2007), pp. 115-126. [3] A. B. Kahng, S. Vaya and A. Zelikovsky, "New graph bipartizations for double-exposure, bright fieldalternating phase-shift mask layout", Proc. Asia and South Pacific Design Automation Conference, 2001, pp. 133-138. UCSD VLSI CAD Laboratory BACUS-2008

  7. Outline • Background • Contributions • DPL Layout Decomposition Flow • DPL Color Assignment Problem Formulation • Experimental Results • Summary UCSD VLSI CAD Laboratory BACUS-2008

  8. DPL Layout Decomposition Flow Layout fracturing Polygons  rectangles Conflict graph construction Projection computation Adjacent nodes connected with conflict edges Node splitting and graph updating Split at all feasible dividing points Update the conflict graph Compute overlap lengths For each pair of touch rectangles, based on projections Color assignment ILP, PCD or NDB based graph bipartization and color assignment Layout fracturing Graph construction Projection computation Node splitting and graph updating Compute overlap lengths ILP/PCD/NDB based color assignment UCSD VLSI CAD Laboratory BACUS-2008

  9. e1 e2 Example: DPL Layout Decomposition • Polygonal layout features  rectangles • Conflict graph construction • Compute projections and feasible dividing points • Node splitting and graph updating • ILP, PCD, or NDB method obtains final coloring solution (b) (a) (d) (c) UCSD VLSI CAD Laboratory BACUS-2008

  10. Outline • Background • Contributions • DPL Layout Decomposition Flow • DPL Color Assignment Problem Formulation • Experimental Results • Summary UCSD VLSI CAD Laboratory BACUS-2008

  11. Min-Cost Color Assignment Problem Given: A list of rectangles R which is color assignable, and maximum distance between two features, t, at which the color assignment is constrained Find: color assignment of rectangles to minimize the total cost Subject to: For any two adjacent non-touching rectangles with 0<d(i,j)≤ t, assign different colors For any two touching rectangles (i.e., d(i,j) = 0), if they are assigned different colors, there is a corresponding cost cij where,d(i,j) = distance between features of i and j t = minimum color spacing between features of i and j UCSD VLSI CAD Laboratory BACUS-2008

  12. Fracturing and Conflict Graph Construction Given a layout, a rectangular layout is obtained by fracturing polygons into rectangles Minimum-sliver fracturing [1] Easier feature operations Avoids design rule violation Given a rectangular layout, construct the conflict graph G =(V, EC ET) Node n represents a feature Conflict edge eci,j:non-touching features ni and nj within distance t Touching edge eti,j: touching features ni and nj n4 n5 n6 n3 n1 n2 et1,2 et3,4 et4,5 et2,3 ec1,3 ec3,5 ec5,6 horizontal vertical min-sliver [1] A. B. Kahng, X. Xu and A. Zelikovsky, “Fast Yield-Driven Fracture for Variable Shaped-Beam Mask Writing", Proc. SPIE Conf. on Photomask and Next-Generation Lithography Mask Technology, 2006, pp. 62832R-1 - 62832R-9. UCSD VLSI CAD Laboratory BACUS-2008

  13. Node Splitting and Graph Updating d < t nl nj d < t nk no dividing point ni nl nj np oq,p op,q nq dividing point nk ni Case (1) Case (2) • Split all nodes with feasible dividing points • Update conflict graph • Conflict graph may not be two-colorable after node splitting • Two cases • Overlap length less than overlap margin • No dividing point with nonzero overlap length • Minimized conflict edges are deleted • Design change: preferentially between features of different cell instances • ILP/PCD/NDB based method for graph bipartization UCSD VLSI CAD Laboratory BACUS-2008

  14. Method 1: ILP Based Min-Cost Color Assignment • xi: binary variable (0/1) for the color of rectangle ri • yij: binary variable for touching edge etij ET • yij = 0 when xi = xj • yij = 1 when xi xj • zij: binary variable for conflict edge ecij EC • zij = 0 when xi xj • zij = 1 when xi = xj • Minimize: • Subject to: • lij: length of rectangle edge of ri opposite to the touching edge between ri and rj • FSmin: minimum feature size • Lij: overlap length between touching rectangles ri and rj • OM: required overlap margin UCSD VLSI CAD Laboratory BACUS-2008

  15. Method 2: Phase Conflict Detection Based Graph Coloring conflict edge e1 e2 touching edge Conflict graph feature edge e1 e2 conflict edge Conflict cycle graph • Gadget based approach: optimal edge-deletion bipartization for planar graph [1] • Two main steps • Heuristic planar graph embedding • Optimal conflict removal for planar graph • Conflict graph  conflict cycle graph • Conflict (green) edge  feature (red) edge • Touching (blue) edge  conflict (black) edge • Edge cost • Conflict edge:   design change • Touching edge  cut and overlap length • /2: design rule or OL violation • +/OLij: no design rule or OL violation • Output: deleted edges with two-colorable graph [1] C. Chiang, A. B. Kahng, S. Sinha, X. Xu, and A. Zelikovsky, "Fast and Efficient Bright-Field AAPSM Conflict Detection and Correction", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 26(1) (2007), pp. 115-126. UCSD VLSI CAD Laboratory BACUS-2008

  16. Method 3: Node-Deletion Bipartization Based Graph Coloring conflict edge e1 e2 touching edge Conflict graph feature edge n1 n2 new node conflict edge Conflict cycle graph • Node-deletion graph bipartization [1] • Conflict cycle graph construction • Conflict (green) edge  new node, feature (red) and conflict (black) edge • Touching (blue) edge new node and two feature (red) edges • Only newly inserted nodes are deletable • Cost of new nodes: same as in PCD • Output: deleted nodes • Map back to conflict and touching edges • After PCD or NDB step, color with breadth first search (BFS) based process [1] A. B. Kahng, S. Vaya, A. Zelikovsky, "New Graph Bipartizations for Double-Exposure, Bright Field Alternating Phase-Shift Mask Layout", Proc. Asia and South Pacific Design Automation Conference, 2001, pp. 133-138. UCSD VLSI CAD Laboratory BACUS-2008

  17. Layout Partitioning Conflict graph is sparse: due to poly-to-cell boundary and whitespace Many islands found in the conflict graph Layout partitioning Partitions conflict graph into connected components Each component has separate conflict graph No edges or nodes of a polygon occur in multiple components Color each component separately Final solution: union of solutions for all components Improves runtime and memory efficiency UCSD VLSI CAD Laboratory BACUS-2008

  18. Outline • Background • Contributions • DPL Layout Decomposition Flow • DPL Color Assignment Problem Formulation • Experimental Results • Summary UCSD VLSI CAD Laboratory BACUS-2008

  19. Testcases • AES: real-world design • Top-B, Top-C, Top-D • Artificial designs • >600 types of cell masters • Artisan 90nm libraries • Placement: 70% and 90% utilization • Minimum design rule: GDS scaled down by 0.4x • Minimum spacing:140nm  56nm • Minimum width: 100nm  40nm UCSD VLSI CAD Laboratory BACUS-2008

  20. ILP Results • Sweep t and placement utilization • Various metrics: deleted conflict edges, overlap length and number of cuts • Minimum overlap length  overlap margin 8nm • No design rule violation UCSD VLSI CAD Laboratory BACUS-2008

  21. PCD Results • Sweep t and placement utilization • Various metrics: deleted conflict edges, overlap length and number of cuts • Minimum overlap length  overlap margin 8nm • No design rule violation UCSD VLSI CAD Laboratory BACUS-2008

  22. NDB Results • Sweep t and placement utilization • Various metrics: deleted conflict edges, overlap length and number of cuts • Minimum overlap length  overlap margin 8nm • No design rule violation UCSD VLSI CAD Laboratory BACUS-2008

  23. Comparison (1) • Higher priority on deleted edges  design changes • Deleted edges: ILP < PCD < NDB • Same deleted edges: ILP obtains minimal cuts with maximal overlap length UCSD VLSI CAD Laboratory BACUS-2008

  24. Comparison (2) • Same deleted edges: ILP obtains larger mean overlap length • Solution quality: ILP > PCD > NDB • Runtime: ILP > NDB > PCD UCSD VLSI CAD Laboratory BACUS-2008

  25. Outline • Background • Contributions • DPL Layout Decomposition Flow • DPL Color Assignment Problem Formulation • Experimental Results • Summary UCSD VLSI CAD Laboratory BACUS-2008

  26. Summary Three approaches: ILP, PCD and NDB methods Address DPL layout decomposition at 45nm and below Improve overlap length and lithography yield Experimental results are promising Overlap lengths  overlap margin Report all necessary design changes Ongoing work Optimal timing/power model guardbanding under bimodal CD distribution in DPL Variability-aware DPL layout decomposition cost function Minimize difference between pitch distributions of two masks Minimize number of distinct DPL layout solutions across all instances of same master cell Balanced mask layout density Integration of forbidden pitch intervals UCSD VLSI CAD Laboratory BACUS-2008

  27. Thank you! UCSD VLSI CAD Laboratory BACUS-2008

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