1 / 68

Computer Architecture I: Digital Design Dr. Robert D. Kent

Explore the design of decoders, address bus networks, and data transformations in digital logic circuits. Learn about N-to-2N decoders and simple decoder configurations. Enhance your understanding of Boolean algebra and MSI design principles.

dkimberley
Download Presentation

Computer Architecture I: Digital Design Dr. Robert D. Kent

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Computer Architecture I: Digital Design Dr. Robert D. Kent Logic Design Decoders and Multiplexers

  2. Review • We have begun to study logic design in the contexts of Medium Scale Integration (MSI) of gate devices and programmable logic devices (PLD). • We have studied the design of a number of specific, practical functional circuits, expressed in terms of Boolean expressions and their equivalent logic gates (SSI: Small Scale Integration) with a view to re-using those circuits as components in MSI design. • 1-bit Half-Adder 1-bit Full-Adder • Multi-bit Ripple Adder Subtractor • Decade Adder Comparator

  3. Goals • We continue our study of simple, but functional Combinational circuits, namely Decoders/Encoders, Multiplexers, and PLD/PLA circuits: • we continue constructing a small library of useful components • through study of the solution process using Boolean algebra and Boolean calculus (simplification, etc.) we better understand the meaning of SSI design • we seek to identify these components for their re-use potential • through our study we will better understand how MSI increases the level of abstraction in solving problems - SSI design is relatively concrete.

  4. Circuit # 9 : Decoders

  5. Circuit # 9 : Decoders • Decoders are most often used to transform one type of coding to another. • Change data representations • Design of address bus networks (specify an address to obtain data)

  6. Circuit # 9 : Decoders • Decoders are most often used to transform one type of coding to another. • Change data representations • Design of address bus networks • A decoder is a multi-input, multi-output logic network.

  7. Circuit # 9 : Decoders N-to-2N0 DEC 01 12 2. .. .. .N-1 2N-1 • Decoders are most often used to transform one type of coding to another. • Change data representations • Design of address bus networks • A decoder is a multi-input, multi-output logic network. • Typically with N inputs and 2N outputs.

  8. Circuit # 9 : Decoders N-to-2N0 DEC 01 12 2. .. .. .N-1 2N-1 • Decoders are most often used to transform one type of coding to another. • Change data representations • Design of address bus networks • A decoder is a multi-input, multi-output logic network. • Typically with N inputs and 2N outputs. • Other types of N-to-M decoders are alsoused, where M < 2N.

  9. Circuit # 9a : Simple Decoder • The simplest decoder has N inputs and 2N outputs. • The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0.

  10. Circuit # 9a : Simple Decoder • The simplest decoder has N inputs and 2N outputs. • The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0. • Example: a 2-line input to 4-line output decoder

  11. Circuit # 9a : Simple Decoder • The simplest decoder has N inputs and 2N outputs. • The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0. • Example: a 2-line input to 4-line output decoderTruth table: Label the outputs DK, noting that the subscript value, K, is just the (unsigned) binary value Kradix-2 = [x1 x0]. Only one output line = 1 at a time.x1 x0 D0 D1 D2 D3 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1

  12. Circuit # 9a : Simple Decoder • The simplest decoder has N inputs and 2N outputs. • The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0. • Example: a 2-line input to 4-line output decoderTruth table: Label the outputs DK, noting that the subscript value, K, is just the (unsigned) binary value Kradix-2 = [x1 x0]. Only one output line = 1 at a time.x1 x0 D0 D1 D2 D3 0 0 1 0 0 0 D0 = x1’ x0’ 0 1 0 1 0 0 D1 = x1’ x01 0 0 0 1 0 D2 = x1 x0’ 1 1 0 0 0 1 D3 = x1 x0

  13. Circuit # 9a : Simple Decoder 2-to-4 DEC D0 D1 D2 D3 X0X1 • The simplest decoder has N inputs and 2N outputs. • The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0. • Example: a 2-line input to 4-line output decoderD0 = x1’ x0’D1 = x1’ x0D2 = x1 x0’ D3 = x1 x0

  14. Circuit # 9a : Simple Decoder Note: Buffer-Inverter= 2-to-4 DEC D0 D1 D2 D3 X0X1 • The simplest decoder has N inputs and 2N outputs. • The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0. • Example: a 2-line input to 4-line output decoderD0 = x1’ x0’D1 = x1’ x0D2 = x1 x0’ D3 = x1 x0

  15. Circuit # 9b : Simple Decoder • The simplest decoder has N inputs and 2N outputs. • The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0. • We consider the example of a 3-input, 8-output decoder.

  16. Circuit # 9b : Simple Decoder • The simplest decoder has N inputs and 2N outputs. • The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0. • We consider the example of a 3-input, 8-output decoder.x2 x1 x0 z0 z1 z2 z3 z4 z5 z6 z70 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1

  17. Circuit # 9b : Simple Decoder • The simplest decoder has N inputs and 2N outputs. • The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0. • We consider the example of a 3-input, 8-output decoder.x2 x1 x0 z0 z1 z2 z3 z4 z5 z6 z70 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1 Note that each output, ZJ, is characterized by a single 1-value that can be immediately represented as a single minterm.

  18. Circuit # 9b : Simple Decoder 3-to-8DEC 00 1 21 3 42 5 6 7 Z0 = X2 X1 X0Z1 = X2 X1 X0 Z2 = X2 X1 X0 Z3 = X2 X1 X0 Z4 = X2 X1 X0 Z5 = X2 X1 X0 Z6 = X2 X1 X0 Z7 = X2 X1 X0 X0X1 X2 • The simplest decoder has N inputs and 2N outputs. • The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0. • We consider the example of a 3-input, 8-output decoder.x2 x1 x0 z0 z1 z2 z3 z4 z5 z6 z70 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1

  19. Circuit # 9b : Simple Decoder 3-to-8DEC 00 1 21 3 42 5 6 7 Z0 = X2 X1 X0Z1 = X2 X1 X0 Z2 = X2 X1 X0 Z3 = X2 X1 X0 Z4 = X2 X1 X0 Z5 = X2 X1 X0 Z6 = X2 X1 X0 Z7 = X2 X1 X0 X0X1 X2 • The simplest decoder has N inputs and 2N outputs. • The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0. • We consider the example of a 3-input, 8-output decoder.x2 x1 x0 z0 z1 z2 z3 z4 z5 z6 z70 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1 minterms

  20. Circuit # 9b : Simple Decoder • The decoder that we have developed is called a minterm generator decoder.

  21. Circuit # 9b : Simple Decoder • The decoder that we have developed is called a minterm generator decoder. • This type of MSI circuit is particularly valuable for constructing other types of circuits, based on the use of minterm expressions:

  22. Circuit # 9b : Simple Decoder • The decoder that we have developed is called a minterm generator decoder. • This type of MSI circuit is particularly valuable for constructing other types of circuits, based on the use of minterm expressions: • Example: Consider two functionsF(X2 X1 X0) = Sum m(1,2,4,5)G(X2 X1 X0) = Sum m(1,5,7)

  23. Circuit # 9b : Simple Decoder • The decoder that we have developed is called a minterm generator decoder. • This type of MSI circuit is particularly valuable for constructing other types of circuits, based on the use of minterm expressions: • Example: Consider two functionsF(X2 X1 X0) = Sum m(1,2,4,5)G(X2 X1 X0) = Sum m(1,5,7) • These can be constructed immediately using the decoderand or gates.

  24. Circuit # 9b : Simple Decoder 3-to-8DEC 00 1 21 3 42 5 6 7 X0X1 X2 F G • The decoder that we have developed is called a minterm generator decoder. • This type of MSI circuit is particularly valuable for constructing other types of circuits, based on the use of minterm expressions: • Example: Consider two functionsF(X2 X1 X0) = Sum m(1,2,4,5)G(X2 X1 X0) = Sum m(1,5,7) • These can be constructed immediately using the decoderand or gates.

  25. Circuit # 9c : Simple Decoder • We note that various functions can be transformed from one form to another.

  26. Circuit # 9c : Simple Decoder • We note that various functions can be transformed from one form to another. • For example: H(X2 X1 X0) = Sum m(0,3,6,7)

  27. Circuit # 9c : Simple Decoder • We note that various functions can be transformed from one form to another. • For example: H(X2 X1 X0) = S m(0,3,6,7) = S m(0,3,6,7) double complement

  28. Circuit # 9c : Simple Decoder • We note that various functions can be transformed from one form to another. • For example: H(X2 X1 X0) = S m(0,3,6,7) = S m(0,3,6,7) double complement = S m(1,2,4,5) complement canonical minterm

  29. Circuit # 9c : Simple Decoder • We note that various functions can be transformed from one form to another. • For example: H(X2 X1 X0) = S m(0,3,6,7) = S m(0,3,6,7) double complement = S m(1,2,4,5) complement canonical minterm = F(X2 X1 X0)

  30. Circuit # 9c : Simple Decoder 3-to-8DEC 00 1 21 3 42 5 6 7 X0X1 X2 H G • We note that various functions can be transformed from one form to another. • For example: H(X2 X1 X0) = S m(0,3,6,7) = G m(0,3,6,7) double complement = S m(1,2,4,5) complement canonical minterm = F(X2 X1 X0)

  31. Circuit # 9c : Simple Decoder 3-to-8DEC 00 1 21 3 42 5 6 7 X0X1 X2 H G • We note that various functions can be transformed from one form to another. • For example: H(X2 X1 X0) = S m(0,3,6,7) = G m(0,3,6,7) double complement = S m(1,2,4,5) complement canonical minterm = F(X2 X1 X0) Note the inverter on the output H, equivalent to using a nor gate.

  32. Circuit # 9d : Decoders with Enable Input • Normally, decoders have one or more additional input lines referred to as enable inputs. • These line values determine whether the circuit is operational or not.

  33. Circuit # 9d : Decoders with Enable Input • Normally, decoders have one or more additional input lines referred to as enable inputs. • These line values determine whether the circuit is operational or not. • Example: a 2-to-4 decoder with enable inputTruth table: Outputs DK can only have value 1 if enabled, E = 1.E x1 x0 D0 D1 D2 D3 0 - - 0 0 0 0 Note: x1 x0 don’t matter1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 1

  34. Circuit # 9d : Decoders with Enable Input • Normally, decoders have one or more additional input lines referred to as enable inputs. • These line values determine whether the circuit is operational or not. • Example: a 2-to-4 decoder with enable inputTruth table: Outputs DK can only have value 1 if enabled, E = 1.E x1 x0 D0 D1 D2 D3 0 - - 0 0 0 0 Note: x1 x0 don’t matter1 0 0 1 0 0 0 D0 = E x1’ x0’ 1 0 1 0 1 0 0 D1 = E x1’ x01 1 0 0 0 1 0 D2 = E x1 x0’ 1 1 1 0 0 0 1 D3 = E x1 x0

  35. Circuit # 9d : Decoders with Enable Input 2-to-4 DEC D0 D1 D2 D3 X0X1 On(1)Off(0) E • Example: a 2-to-4 decoder with enable inputD0 = E x1’ x0’D1 = E x1’ x0D2 = E x1 x0’ D3 = E x1 x0

  36. Circuit # 9d : Decoders with Enable Input 2-to-4 DEC D0 D1 D2 D3 X0X1 D0 D1 D2 D3 2-to-4DEC X0X1 On(1)Off(0) E E • Example: a 2-to-4 decoder with enable inputD0 = E x1’ x0’D1 = E x1’ x0D2 = E x1 x0’ D3 = E x1 x0

  37. Circuit # 9e : Decoder as LED Controller • We now consider using a decoder to control the output of a set of light emitting diodes (LED’s) that display a decimal digit. LEDdigit

  38. Circuit # 9e : Decoder as LED Controller • We now consider using a decoder to control the output of a set of light emitting diodes (LED’s) that display a decimal digit. • We use a 4-to-7 decoder with enable input (E = 1 ON, E = 0 OFF) LEDdigit 0 1 2 3 4 5 6

  39. Circuit # 9e : Decoder as LED Controller 0 1 2 3 4 5 6 • We now consider using a decoder to control the output of a set of light emitting diodes (LED’s) that display a decimal digit. • We use a 4-to-7 decoder with enable input (E = 1 ON, E = 0 OFF)E x3 x2 x1 x0 z0 z1 z2 z3 z4 z5 z60 - - - - 0 0 0 0 0 0 0 LEDdigit

  40. Circuit # 9e : Decoder as LED Controller 0 1 2 3 4 5 6 • We now consider using a decoder to control the output of a set of light emitting diodes (LED’s) that display a decimal digit. • We use a 4-to-7 decoder with enable input (E = 1 ON, E = 0 OFF)E x3 x2 x1 x0 z0 z1 z2 z3 z4 z5 z60 - - - - 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 LEDdigit

  41. Circuit # 9e : Decoder as LED Controller 0 1 2 3 4 5 6 • We now consider using a decoder to control the output of a set of light emitting diodes (LED’s) that display a decimal digit. • We use a 4-to-7 decoder with enable input (E = 1 ON, E = 0 OFF)E x3 x2 x1 x0 z0 z1 z2 z3 z4 z5 z60 - - - - 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 1 1 0 1 1 0 1 1 LEDdigit

  42. Circuit # 9e : Decoder as LED Controller 0 1 2 3 4 5 6 • We now consider using a decoder to control the output of a set of light emitting diodes (LED’s) that display a decimal digit. • We use a 4-to-7 decoder with enable input (E = 1 ON, E = 0 OFF)E x3 x2 x1 x0 z0 z1 z2 z3 z4 z5 z60 - - - - 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 1 1 0 1 1 0 1 11 0 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 1 LEDdigit

  43. Circuit # 9e : Decoder as LED Controller 0 1 2 3 4 5 6 • We now consider using a decoder to control the output of a set of light emitting diodes (LED’s) that display a decimal digit. • We use a 4-to-7 decoder with enable input (E = 1 ON, E = 0 OFF)E x3 x2 x1 x0 z0 z1 z2 z3 z4 z5 z60 - - - - 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 1 1 0 1 1 0 1 11 0 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 11 0 1 1 0 0 1 0 1 1 1 1 1 0 1 1 1 1 0 1 0 0 1 01 1 0 0 0 1 1 1 1 1 1 1 LEDdigit

  44. Circuit # 9e : Decoder as LED Controller 0 1 2 3 4 5 6 • We now consider using a decoder to control the output of a set of light emitting diodes (LED’s) that display a decimal digit. • We use a 4-to-7 decoder with enable input (E = 1 ON, E = 0 OFF)E x3 x2 x1 x0 z0 z1 z2 z3 z4 z5 z60 - - - - 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 1 1 0 1 1 0 1 11 0 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 11 0 1 1 0 0 1 0 1 1 1 1 1 0 1 1 1 1 0 1 0 0 1 01 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 0 LEDdigit

  45. Circuit # 9e : Decoder as LED Controller • We obtain the canonical minterm expressions:E x3 x2 x1 x0 z0 z1 z2 z3 z4 z5 z60 - - - - 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 1 1 0 1 1 0 1 11 0 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 11 0 1 1 0 0 1 0 1 1 1 1 1 0 1 1 1 1 0 1 0 0 1 01 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 0

  46. Circuit # 9e : Decoder as LED Controller Z0 = S m(0,2,3,5,7,8,9) Z1 = S m(0,4,5,6,8,9) Z2 = S m(0,1,2,3,4,7,8,9) Z3 = S m(2,3,4,5,6,8,9) Z4 = S m(0,2,6,8) Z5 = S m(0,1,2,4,5,6,7,8,9) Z6 = S m(0,2,3,5,6,8) • We obtain the canonical minterm expressions:E x3 x2 x1 x0 z0 z1 z2 z3 z4 z5 z60 - - - - 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 1 1 0 1 1 0 1 11 0 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 11 0 1 1 0 0 1 0 1 1 1 1 1 0 1 1 1 1 0 1 0 0 1 01 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 0

  47. Circuit # 9e : Decoder as LED Controller Z0 = S m(0,2,3,5,7,8,9) Z1 = G m(0,4,5,6,8,9) Z2 = G m(0,1,2,3,4,7,8,9) Z3 = G m(2,3,4,5,6,8,9) Z4 = G m(0,2,6,8) Z5 = G m(0,1,2,4,5,6,7,8,9) Z6 = G m(0,2,3,5,6,8) Z0’ = S m(1,4,6) Z1’ = S m(1,2,3,7) Z2’ = S m(5,6) Z3’ = S m(0,1,7) Z4’ = S m(1,3,4,5,7,9) Z5’ = S m(3) Z6’ = S m(1,4,7,9) • And simplify, if possible (e.g. using complementation):E x3 x2 x1 x0 z0 z1 z2 z3 z4 z5 z60 - - - - 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 1 1 0 1 1 0 1 11 0 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 11 0 1 1 0 0 1 0 1 1 1 1 1 0 1 1 1 1 0 1 0 0 1 01 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 0

  48. Circuit # 9e : Decoder as LED Controller 4-to-10DEC 00 11 22 33 4 5 6 7 8 9 Z0’Z1’Z2’Z3’Z4’Z5’Z6’ X0X1X2X3E Z0’ = S m(1,4,6) Z1’ = S m(1,2,3,7) Z2’ = S m(5,6) Z3’ = S m(0,1,7) Z4’ = S m(1,3,4,5,7,9) Z5’ = S m(3) Z6’ = S m(1,4,7,9) 0 1 2 3 4 5 6

  49. Circuit # 10 : Encoders

  50. Circuit # 10 : Encoders 2N-to-N0 ENC 01 12 2. .. .. .2N-1 N-1 N-to-2N0 DEC 01 12 2. .. .. .N-1 2N-1 • Encoders are essentially the inverse of decoders. • Typical encoders are represented as 2N input lines to N output lines. • In general, encoders are N-to-M decoders, where N > M.

More Related