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FEE for testbeam

FEE for testbeam. Physics prototype : FEE status. FLC_PHY3 ASIC status 1000 + 1600 chips produced AMS 0.8µm BiCMOS (yield 80%) 1600 chips now at packaging (most for Korea). 6x6 1 cm 2 photodiode wafers. Calibration ASIC. FLC_PHY3 18ch readout ASIC. PCBoards

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FEE for testbeam

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  1. FEE for testbeam

  2. Physics prototype : FEE status • FLC_PHY3 ASIC status • 1000 + 1600 chips produced • AMS 0.8µm BiCMOS (yield 80%) • 1600 chips now at packaging (most for Korea) 6x6 1 cm2 photodiode wafers Calibration ASIC FLC_PHY3 18ch readout ASIC • PCBoards • 95 boards already produced (14 in used in the proto) • 70 are needed to equip the proto • 20 more spares being produced (10 full, 5 left and 5 right PCBs) • PCBs in hand, assembly & test in Nov-Dec 2005 C. de La Taille FEE for testbeam

  3. Physics prototype news • Power supply regulating boards • 70 Produced • Tested : 60 needed, 67 good • Features : • prevent voltage surge on front-end supply • Regulate front-end supply • Filter high-voltage supply • New power supplies in hand • 3* Lambda 8V / 80Amps • GPIB for slow control • Will pass DESY safety control • What remains to be done • Electronics analysis in testbeam • Noise (white and coherent) • Stability (baseline and gain) • Crosstalk • Strange effects (if any) Baseline variation [G. Mavromanolakis] Noise, MIP [G. Gaycken] C. de La Taille FEE for testbeam

  4. Ch.1 1 Multiplexing Gain 10 Multiplexing Gain 1 10 Bi-gain => Full dynamic range Ch.2 Ch.18 Digital Output 12 bit ADC ( AMS IP) Digital Output Idle Next steps with physics prototype : FLCPHY4 • ASIC submitted in july 05 Power Cycling C. de La Taille FEE for testbeam

  5. RFCF signal Log scales ! ON 20 µs Ready for pulse Preamp output at power up FLCPHY4 : main issues • Mixed signal issues • Digital activity with sensistive analog front-end • Pulsed power issues • Electronics stability • Thermal effects • No external components • Reduce PCB thickness to 800µm • Internal supplies decoupling C. de La Taille FEE for testbeam

  6. Design of ILC_FEV4 • New PCBs (ILC_FEV4) • Chip in the detector • Ultra-thin PCB • Test 3 boards in physics prototype • Need to adapt DAQ • Digital data in • Power pulsing 1750µm diodes+ FE electronic PCB (600µm) Wafer (500µm) FE chip (1mm) C. de La Taille FEE for testbeam

  7. FEE for HCAL testbeam • AHCAL ASIC : ILC_SiPM • 800 chips produced • Looks OK • New version for technological prototype will be studied beg 06 • DHCAL ASIC • First prototype received by FNAL, now under test • Iteration foreseen beg 06 • Prototype for technological prototype will be studied by in2p3 C. de La Taille FEE for testbeam

  8. Conclusion • Front-end electronics completed for test beam ECAL & AHCAL prototypes • Power pulsing to be tested on testbench then in testbeam on a few boards in 2006 • More effort needed on ADCs C. de La Taille FEE for testbeam

  9. Spare slides C. de La Taille FEE for testbeam

  10. R&D on ADCs • Pipeline ADC V3 [S. Manen] • 10bit 5MHz 8mW • New version submitted jun 05, just received • Fixing non linearity and stability pb • SAR ADC C/2C [L. Raux] • 10bits 1 MHz 1mW • Submitted in dec 04, under test • Wilkinson [J. Fleury] • 12bit 10kHz 2.5mW • Submitted in dec 04, waiting for test • SAR ADC [L. Raux] • 12 bit 1MHz 3 mW • Submitted july 05, arriving soon • Still a long way to go… • 10 bits or 12 bits ? Measured linearity of Pipeline 10 bit ADC Layout of Wilkinson 12bit ADC C. de La Taille FEE for testbeam

  11. FLC_PHY4 design • Analog front-end : • Same preamplifier as FLCTECH1 • Extended dynamic range CF->10pF • Shaper bi-gain G1-G10 • Power pulsing • Differential Track&Hold + multiplexer • Internal bias • ADC : 12 bit 1MHz 8mW • Commercial IP from AMS to start with • 18 channels, Pd = 2mW + 8mW ADC • To be submitted April 05 in AMS 0.35µ • What is still missing • SCA • Zero suppress C. de La Taille FEE for testbeam

  12. Towards module0 ASIC : ILC_TECH2 • ILC_TECH2 : 2 channels with autotrigger • 2 designs : continuous time shaper (LAL), gated integrator (LPC) Power Cycling Auto-trigger on ½ MIP Internal ADC C. de La Taille FEE for testbeam

  13. Workplan for 2006 • Physics prototype • Analysis of TB at DESY : electronics performance : physicist inputs needed • Test new thin PCB with FLCPHY3 ASIC inside detector & inside shower • Test power pulsing with new FLCPHY4 on testbeam data • Technological prototype • Optimize detector geometry (cell size, #layers…) : physicist inputs needed NB : directly impacts front-End ASIC design • Finalize ILC_TECH2-3 front-end ASIC, including digital part and readout scheme • Advance in parallel R&D on ADCs • Design “stitchable” motherboards • Prototype front end ASICs for AHCAL and/or DHCAL • Participate to construction of technological prototype within EUDET C. de La Taille FEE for testbeam

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