Computer Architecture Memory: SRAM, DRAM

Computer ArchitectureMemory: SRAM, DRAM Lynn Choi Dept. Of Computer and Electronics Engineering

SRAM Operation • Individual bits are D latches, not edge-triggered D flip-flops. • Fewer transistors per cell. • Implications for write operations: • Address must be stable before writing cell. • Data must be stable before ending a write.

SRAM Cell • Six transistors per cell WRITE: 1. Drive bit lines 2. Select row READ: 1. Precharge bit lines 2. Select row 3. Sense amp detects difference between bit lines

SRAM • SRAM control signals • CS (Cheap Select) • OE (Output Enable) • WE (Write Enable)

SRAM Array

Bidirectional In and Out Data Pins • Use the same data pins for reads and writes • Especially common on wide devices • Makes sense when used with microprocessor buses (also bidirectional)

SRAM Devices

DRAM Cell • 1 transistor per cell • DRAM read operation • Precharge bit line to VDD/2. • Take the word line HIGH. • Detect whether current flows into or out of the cell. • Cell contents are destroyed by the read! • Must write the bit value back after reading. • DRAM write operation • Take the word line HIGH. • Set the bit line LOW or HIGH to store 0 or 1. • Take the word line LOW. • The stored charge for a 1 will eventually leak off.

DRAM Refresh • Typical devices require each cell to be refreshed once every 4 to 64 mS. • During “suspended” operation, notebook computers use power mainly for DRAM refresh.

DRAM Chip Internal Organization • 64K x 1 bit DRAM

RAS/CAS Operation • Row Address Strobe, Column Address Strobe • n address bits are provided in two steps using n/2 pins, referenced to the falling edges of RAS_L and CAS_L • Traditional method of DRAM operation for 20 years. • Now being supplanted by synchronous, clocked interfaces in SDRAM (synchronous DRAM). • DRAM read timing

DRAM Timing • DRAM write timing • DRAM refresh timing

DRAM access modes • Fast Page Mode • Page: All bits on the same ROW (Spatial Locality) • Don’t need to wait for word line to recharge • RAS, then any CAS (row buffer acts as a page cache) • Hence, after RAS, the row is randomly addressable • Access time in 60ns - 120 ns, for slower than 66MHz bus • EDO (Extended Data Out), Burst EDO • A second memory reference begins before the previous memory reference completes (pipelining) • for 66 MHz bus, comes with SIMM • Synchronous DRAM • Address and data lines are driven by a single clock • No wait time and for greater than100 MHz bus • Rambus DRAM • Packet-based interface, pipelined, better transmission line characteristics allows higher speed signaling

DRAM Packaging • Typically, 8 or 16 memory chips are mounted on a tiny printed circuit board • For compatibility and easier upgrade • SIMM (Single Inline Memory Module) • Connectors on one side • 32 pins for 8b data bus • 72 pins for 32b data bus • DIMM (Dual Inline Memory Module) • For 64b data bus (64, 72, 80) • 84 pins at both sides, total of 168 pins • Ex) 16 16M*4 bit DRAM constitutes 128MB DRAM module with 64b data bus • SO-DIMM (Small Outline DIMM) for notebooks • 72 pins for 32b data while 144pins for 64b data bus

Computer Architecture Memory: SRAM, DRAM