1 / 13

Calorimeter Trigger Link Updates

Calorimeter Trigger Link Updates. Instalacao Cabos SLB (USC55). TO DO list. Instalacao Cabos SLB (USC55). TO DO list. Trigger Links Upgrade. TO DO list. Clearly …no more cables…so no more SLBs. SLB : Lets’ go…Optical. TO DO list. SLBs embedded on Trigger FPGAs

draco
Download Presentation

Calorimeter Trigger Link Updates

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Calorimeter Trigger Link Updates

  2. Instalacao Cabos SLB (USC55) TO DO list

  3. Instalacao Cabos SLB (USC55) TO DO list

  4. Trigger Links Upgrade TO DO list • Clearly …no more cables…so no more SLBs

  5. SLB : Lets’ go…Optical TO DO list • SLBs embedded on Trigger FPGAs • High Speed Transceivers FPGAs • Xilinx or Altera , 3, 125 GB/s up to 6 GB/s • 20/24 channels per FPGA • Higher Speed > less Trigger Links • from a TCC /HTR to the RCT • New TCCs, New RCT Receiver Card Design

  6. SLB : Lets’ go…Optical TO DO list • Extra Latency (?) on trigger path (link lock timing) • Partially recovered • Aligning pattern techniques • 1st data markers, Data Headers identifiers

  7. Trigger Primitives flow TO DO list • Presently we do : • Parallel to serial in the SM • Serial to Parallel on the TCC/HTR • Parallel to serial on the SLB • Serial to parallel to serial on the RTC • Why are we torturing the poor data for?

  8. Reduce Interfaces ? TO DO list • IF we merge SLB into the TCC FPGAs with High Speed Links… • New TCCs (HTRs) • No more SLB boards • New RCT Receiver Cards • Parallel to serial in the SM • Serial to Serial on the TCC (HTR) • Parallel to serial on the SLB • Serial to parallel to serial on the RTC • Ok, we got one interface out ….can we do better?

  9. Can this get better? TO DO list • HTR/TCC/RCT design? • Covers the same detector region • Number of input optical links *68 x 2? • FPGAs decoding Schemes …(8b/10b) • To much “variables” • A Common PCB Design for HCAL and ECAL

  10. IF we Redesign of the SM FE board TO DO list • Merge Trigger and Data on the same links (1.6 GB/s) • Interleaved Data transmission (Channel A-B) • TCC/RCT with DCC functionality… • No more DCCs… no more TCC to DCC links…

  11. Design Issues TO DO list • Number channels per board • Housing of links, number of FPGAs, • Clock fanout , Very Low Jitter • POWER on boards • We can have up to 10 A per FPGA

  12. Design responsibilities shared TO DO list • Each Group maintains FPGA code responsibility • Design core boundaries, not PCBs • A PCB Design from a common group • Costs of production and assembly shared by groups • can we loose the “which is my board” complex?

  13. Conclusions TO DO list • We can go on to several levels of redesign/integration: • TCC and RCT design, SLB Embedded, 1st Level • TCC/HTR/RCT, 2nd Level • SM FEB redesign, TCC/RCT/DCC design ,3rd Level • ECAL /HCAL FE Redesign… • 4th Level

More Related