An Effective DFM Strategy Requires Accurate Process and IP Pre-Characterization

2. An Effective DFM Strategy Requires Accurate Process and IP Pre-Characterization Carlo Guardiani, Massimo Bertoletti, Nicola Dragone, Marco Malcotti, and Patrick McNamara PDF Solutions Inc. DAC 2005, Anaheim, CA

3. Technology Roadmap Challenges 45nm • Lithography • Layout pattern dependence • Immersion litho, • OPC/PSM integration w/ photo window • Front end/Transistor • New gate/oxide architectures • Reliability 65nm • Lithography • OPC/PSM integr. w/ photo-window • Front-end/Transistor • Layout dependent performance • Parametric variation 90nm • Back-end integration • Low-k • CMP • Product ramp issues • Yield vs. performance

4. The Evolution of Product Yields • Random defects are no longer the dominant yield loss mechanism • Yields are limited by design features

5. Accurate Yield Models Characterizedin Silicon Fully integrated in standard design tools and flows Design rules guarantee yield!…well, not really… …then recommended rules …and opportunistic design data base post-processing to enforce them From Reactive to Proactive DFM: A Copernican Revolution… Yield Revolved Around Rules Yield Models are the driving force in the DFM universe

6. 32 FPB MUX4X1AFY_Y1 - 20 tracks 25 FPB MUX4X1AFY_PMSY4 - 21 tracks MUX4X1AFY_COY4 - 25 tracks 20 FPB MUX4X1AFY1_Y16 - 27 tracks 19 FPB Rule-based DFM?

7. Design Verification Verification Verification Verification Design Design IP lib. Design Floorplan Formal Formal Physical Physical Synthesis Place&route DFM sign-off DFM sign-off Statistical Timing & SI Timing & SI DFM & Manufacturing DFM & Manufacturing Design DFM Optimizations Dummy Fill DFM Tuning IP lib. Design Dummy Fill Yield Aware Floorplan MDP OPC/RET Mask Making MDP OPC/RET Mask Making Yield-aware Place&route Yield –aware Synthesis Reactive vs. Proactive DFM Reactive DFM DRM SPICE Pro-Active DFM Manufacturing Facility DRM SPICE

8. Proactive DFM • Designer access to process data is limited • DFM today is Reactive • Increased design cycle time • Risky design feature changes • Misaligned mask GDSII and design database • DFM needs to be Proactive • Up-front accurate process characterization • Occurring early in the design flow • Model based IP characterization • Manufacturable-by-construction designs

9. Library GDS Process FR (D0,l) Litho Process Window Yield Extractions Process Margins and Litho calibration data Library GDS RANDOM Design Attributes Context Generation Golden OPC/RET ACC Lithography Simulator Design SYSTEMATIC .pdfm Library YIMP ACC .pdfm DFM characterization Of IP libraries • Characterize IP library for yield (.pdfm) • Extract design attributes of yield models • Include random, design systematic andlitho effects • New yield library view (.pdfm) • Enable hierarchical large capacity DFM chip analysis

10. Random Yield Loss: Physical Mechanisms Material opens Material shorts Type Yield Loss Mechanisms Random Active, poly and metal shorts and opens due to particle defects Contact and via opens due to formation defectivity

11. Random Yield Loss: Test Structures • Extract Metal layer open and short defectivity • Extract Metal layer open and short Defect Size Distribution (DSD)

12. Systematic Yield Loss: Physical Mechanisms Type Yield Loss Mechanisms Systematic Impact of micro/macro loading design rule marginalities Leakage from STI related stress Contact/via opens due to local neighborhood effects (e.g. pitch/hole size) Misalignment, line-ends/borders

13. To Pad A To Pad B To Pad C M1 STI N+ P+ N+ PWL Systematic Yield Loss: Test Structures Without Neighborhood With Neighborhood

14. Printability Yield Loss: Physical Mechanisms Type Yield Loss Mechanisms Systematic Poor contact coverage due to misalignment and defocus/pull back Poly/Metal shorts Material opens

15. Printability Yield Loss: Modeling Layout Metric Misalignment Mask Error Defocus Exposure Yield Loss coverage

16. The .pdfm View • Library characterized to generate manufacturability view (.pdfm) • Random and design systematic yield • Litho process window • Using calibrated yield models • Multi-layer litho process window incorporated

17. COAO3BTC2NOR2XC_R2 10 8 orig 6 Y1 4 Y2 Cell FR Improvement (ppb) 2 Y3 Y4 0 Y5 Poly Open Poly Open Poly Short Poly Short M1 Open M1 Open M1 Short M1 Short -2 Y6 -4 -6 Process Corner Application: IP library DFM Quality Analysis Yield sensitivity analysis • Optimal design depends on process corner • Ex NAND2: Y5, Y6, Y1, Y4 • Best becomes worst at different process corner • Ex NAND2: Y1_m1opens vs. Y1_m1shorts • DFM Sensitivity depends on layout attributes • M1 more sensitive than Poly • Identify redundant layout implementations • Ex AOI: Y4, Y5 NAND2 CELL Dominant Process Effect AOI CELL Process Corner

18. Yield aware synthesys and place&route • Proactive DFM • Maximize manufacturability by construction RTL Design DFM SW plug-ins Yield View (.pdfm) Hierarchical Floorplan VERIFICATION Yield Gap Yield Yield Models Models Estimation Estimator Physical Synthesis Yield Yield DFM LIBRARIES Extended IP Optimization Optimizer Chip Assembly Sign-off Standard Libraries

19. Conclusions • Impact of design systematic and lithography yield loss mechanisms crossed over random phenomena • Rule-based, reactive DFM is impractical • Model-based, proactive DFM is the answer • Early in the design flow • Find the best trade-off based on actual process capabilities • Before verification