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Processor and Memory organization – Lesson-1 Processor organization

Processor and Memory organization – Lesson-1 Processor organization. 1. The Structural Units in a Processor:. Internal and external buses interconnect the processor internal units with system memories, I/O devices and all other system elements Address, data and control buses.

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Processor and Memory organization – Lesson-1 Processor organization

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  1. Processor and Memory organization – Lesson-1 Processor organization Chapter-2 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  2. 1.The Structural Units in a Processor: Chapter-2 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  3. Chapter-2 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  4. Internal and external buses interconnect the processor internal units with system memories, I/O devices and all other system elements • Address, data and control buses Chapter-2 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  5. MDR (memory data register) holds the accessed byte or word • MAR (memory address register) holds the address • BIU (Bus Interface Unit) • Program Counter or Instruction Pointer and Stack Pointer Chapter-2 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  6. ARS (Application Register Set): Set of on-chip registers for use in the application program. • Register window- a subset of registers with each subset storing static variables and status words of a routine. • Changing windows helps in fast context-switching in a program. Chapter-2 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  7. ALU and FLPU (Arithmetic and Logic operations Unit and Floating Points operations Unit). FLPU associates a FLP register set for operations. • Register set is also called file and associates ALU or FLPU. Chapter-2 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  8. Instruction, Data and Branch Target Caches and associated PFCU (Prefetch control unit) for pre-fetching the instructions, data and next branch target instructions, respectively. • Multi-way Cache – Example- 16 kB, 32-way Instruction cache with 32 byte block for data and 16 kB in ARM • Cache block – Enables simultaneous cache of several memory locations of a set of instructions Chapter-2 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  9. AOU (Atomic Operations Unit ) An instruction is broken into number of processor-instructions called atomic operations (AOs), AOU finishes the AOs before an interrupt of the process occurs - Prevents problems arising out of incomplete processor-operations on the shared data in the programs Chapter-2 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  10. Advanced Processing units – (i) MAC, bit reversal and shifter units, VLIW processing unit in a DSP, (ii) Units for multistage pipeline processing, multi-line superscalar processing to boost the processing speeds much higher than one instruction per clock cycle. Chapter-2 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  11. 2. Processor Performance Measures • MIPS – Million Instructions Per Second • MFLOPS – Million Floating Point Operations Per Second • Dhrystone/s – Number of times a benchmark program called Dhrystone program can run per second.[1MIPS = 1757 Dhrystone/s Chapter-2 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  12. 3. Characteristics considered during Processor Selection in Embedded System • Instruction Cycle Time • Processing Performance per sec per W • Internal Bus Width • Caches and multi-way caches Chapter-2 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  13. On-chip RAM and ROM • Interrupt System • Requirement of Floating Point instructions • Requirement of Bit Manipulations instruction needs Chapter-2 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  14. On-chip DMA controller • Interrupt System • Advanced Processing Units • Harvard or Princeton Architectures for memory organization Chapter-2 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  15. RISC or CISC or RISC core with CISC like instruction set • On-chip compiler, • AOs feasibility • IO Mapped IO space like 80x86 or Memory mapped IOs Chapter-2 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  16. 4. Processor Selection Examples Chapter-2 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  17. 1.Real-Time Control of a Robot • Motor needs signal at the rate of 50 to 100 ms only. Program size is also limited. Low MIPS performance suffices. Therefore, Microcontroller 8051, 68HC11, 68HC12 are the best choice. [Refer Example 2.2 pp. 63 for details] Chapter-2 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  18. 2. Voice Data Compression Voice signals are 64kbps. High MIPS performance needed. On-chip memory does not suffice for the resulting data. Therefore, an exemplary processor needed is 80x86 or a DSP [Refer Example 2.3 pp. 63-64 for details] Chapter-2 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  19. 3. Network Switching System Transfer rates of 100 Mbps from a switch are needed. RISC architecture for high MIPS needed. Exemplary processors needed are Power PC or ARM7. [Refer Example 2.4 pp. 64 for details] Chapter-2 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  20. 4. Real Time Video Processing - Needs fast frame compression - Use of a DSP with advanced Processing units MACs needed. - Multiprocessor system having TMS DSP, SHARC, TigerSHARC, ARM9 or PowerPC processors needed. [Refer Example 2.5 pp. 64 for details] Chapter-2 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  21. Summary We learnt • (i) Structural units in a processor to enable selection of appropriate processor for an embedded System • (ii) Performance Measures for a processor – MIPS, MFLOPS, Dhrystone/s Chapter-2 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  22. We learnt • (iii) Caches , pipelines, superscalar units and RISC processing give high performance • (iv) Voice, audio, video related systems need DSPs or media Processors as these have the special units like MACs for fast execution of VLIWs Chapter-2 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  23. End of Lesson 1 of Chapter 2 Chapter-2 L1: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

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