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CFI - Opto DAQ - Status

CFI - Opto DAQ - Status. 24th February 2005. Gigabit Ethernet. Network IP Core We now have the production release of the core Significantly upgraded including changes to API Testing completed and now in use Multi-project license - purchased. Gigabit Ethernet - Manufacturer Test results.

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CFI - Opto DAQ - Status

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  1. CFI - Opto DAQ - Status 24th February 2005 Engineering & Instrumentation Department, ESDG, Rob Halsall, 24th February 2005 CFI/Confidential

  2. Gigabit Ethernet • Network IP Core • We now have the production release of the core • Significantly upgraded including changes to API • Testing completed and now in use • Multi-project license - purchased Engineering & Instrumentation Department, ESDG, Rob Halsall, 24th February 2005 CFI/Confidential

  3. Gigabit Ethernet - Manufacturer Test results • FPGA - FPGA Flat out • PC - PC 7-800 Mbit/s • FPGA - PC Windows 500 Mbit/s LINUX 600 Mbit/s * results include checking data • FPGA - PC transfer has worse performance for technical reasons • This can be improved... • All results with higher performance network card than we are using Engineering & Instrumentation Department, ESDG, Rob Halsall, 24th February 2005 CFI/Confidential

  4. Gigabit Ethernet - My Test results • FPGA - PC/Windows Only • R&W streaming Loop back 20 M Byte/s • Read streaming 26 M Byte/s • RDMA 12 M Byte/s • Need to repeat tests with better network card • Higher performance cards have been purchased Engineering & Instrumentation Department, ESDG, Rob Halsall, 24th February 2005 CFI/Confidential

  5. Software Histogramming - Tests • Internal to PC Algorithm 1 82 M Words/s Algorithm 2 37 M Words/s Algorithm 3 42 M Words/s Algorithm 4 427 M Words/s • FPGA -> PC 5.6 M Words/s • Can be improved - probably to 20 M Word/s Intel 3.2GHz P4 extreme with 2GB Memory 32 bit words , 12 bit Frame, 20 bit Pseudo Random Data 100 M Pixel Address list, 128 M Word Histogram Memory Engineering & Instrumentation Department, ESDG, Rob Halsall, 24th February 2005 CFI/Confidential

  6. Network Software • Network core API • UNIX based C & library -> windows API C++ & DLL based • LINUX version also available • Matlab • MAPS integrating new code is in progress…some difficulties integrating DLL • C • Test programs implemented in C++ • Labview • Need to look into integrating the DLL • However… Engineering & Instrumentation Department, ESDG, Rob Halsall, 24th February 2005 CFI/Confidential

  7. Network Software • User application can be Matlab, Labview, C, C++,…. • Server application can perform high performance functions such as histogramming • Server & user applications can run on same machine • Development of a basic server application is in progress with Matlab as the user application User App Server App FPGA Ethernet fibre channel usb2 UDP TCP/IP Engineering & Instrumentation Department, ESDG, Rob Halsall, 24th February 2005 CFI/Confidential

  8. 10 Gigabit Ethernet • Progress in acquiring 10G development board • Visited Xilinx UK rocket Labs 26th November • Expect to loan a 10G Development board from Xilinx mid Feb • In progress • Procure 2 Off 10G line cards - ordered • Procure 2 Off High End PCs - ordered • Arrange evaluation license for 10G Ethernet MAC • Write Test Software PCs -> 2 x 3.2GHz Xeon, PCI-X 133, 4GByte RAM (32G max) Engineering & Instrumentation Department, ESDG, Rob Halsall, 24th February 2005 CFI/Confidential

  9. Clock & Trigger distribution • No work done on this as yet • The new Memec P30 should make this much easier to do due to the • extensive use of SFP optical modules • extensive use of external Programmable Clock PLLs & SMA connectors Engineering & Instrumentation Department, ESDG, Rob Halsall, 24th February 2005 CFI/Confidential

  10. Data Processing & Visualisation • No work done on this yet • 1 Week Xilinx Training EDK & DSP from December 13th - completed • Visualisation direct from FPGA will require a new dev board equipped with a VGA/DVI interface Engineering & Instrumentation Department, ESDG, Rob Halsall, 24th February 2005 CFI/Confidential

  11. MAPS/P30 Dev Board Engineering & Instrumentation Department, ESDG, Rob Halsall, 24th February 2005 CFI/Confidential

  12. Project Management • The STP plan in project spec is end loaded • I expect to use the remaining funding in a 4 month block of effort Engineering & Instrumentation Department, ESDG, Rob Halsall, 24th February 2005 CFI/Confidential

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