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The PDM-block

The PDM-block. M. Casolino on behalf of JEM-EUSO collaboration EUSO-BALLOON Phase A review 2 nd February 2012, CNES, Toulouse. PDM Block and the instrument. What is the PDM unit ?.

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The PDM-block

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  1. The PDM-block M. Casolino on behalf of JEM-EUSO collaboration EUSO-BALLOON Phase A review 2nd February 2012, CNES, Toulouse

  2. PDM Block and the instrument

  3. What is the PDM unit ? The PDM, which stands for Photo Detector Module, consists in 36 MAPMTs (grouped in 9 Elementary cells and arranged in matrix of 6x6) equipped with UV filters and their associated electronic chain. The PDM has a well defined mechanical structure that welcome all these elements

  4. Technical specifications FunctionalRequirements It is the core element to detect the UV light coming from the optics. Size 167 mm x 167 mm x 200 mm (TBC) corresponding to the mechanical structure, the MAPMT and electronic (EC_dynode, Ec_anode, EC_HV, EC_ASIC, PDM board, HV box (LVPS + switches)) Mass The total weight is given by the mechanical structure (0,730 kg)+ electronic (~ 1,7 kg) + MAPMT (1,125 Kg) and HV box (300 g TBC) + PDM Board (145 g) + LVPS (150 g). All those numbers are TBC. Power budget About 300 mW for one EC without MAPMT. Therefore 2.7 W for the 9 EC units. HV box is about 800 mW total. The power consumption of the PDM board (1.8 W) and the switches should be added. All those numbers are (TBC).

  5. Mechanical Structure

  6. Mechanics Prototype Prototypes of the PDM structure already manufactured by the INFN- National Laboratories in Frascati, Italy.

  7. PDM unit description • The PhotoMultiplier (MAPMT) and the Filters • The ASIC (ASIC) • The Elementary Cell (EC) • The High Voltage Power Supply (HVPS) and Switches (SW) • The PDM Board (PDMB)

  8. EC boards (P. Barrillon) 9 elements each with 4MAPMTs for a total of 36 MAPMTS

  9. EC ASIC board (P. Barrillon) At least 120 mm needed. 120 pins ~ 20 mm ASIC ASIC ASIC ASIC ASIC ASIC ~40 mm 68 pins 68 pins 68 pins 68 pins 68 pins 68 pins ~ 60 mm ~ 150 mm 6 elements each with 6ASICs on each Total of 36 ASICs 6 connectors to PDM-FPGA board

  10. PDM FPGA board 1 board in the PDM Interfaces to 6ASIC boards Interfaces to CCB board Interface to LV power supply

  11. The PDM Board (PDMB) Functional Requirements, first-level trigger algorithm, and the interface with the EC board and CCB board. Housekeeping and other operation-related functions are also controlled by the FPGA chips. Clocks at 40MHz and 400kHz are received from the CCB and distributed to EC boards. From the EC boards, the data transmission is running at the rate of 400kHz. To the CCB, the data transmission rate is at a lower level, 7Hz (TBC).

  12. LVPS and switches, HV box (P. Gorodetzky)

  13. Risk analysis EC boards not available in due time Mechanical integration problems Delay in PDM assembly/integration Electronics integration problems Common noise Grounding loops Failure of 1 component (EC, HV, PDM, ASIC after integration…) Maquette and electrical protype needed Spares need to be produced. Help will come from TA-EUSO experiment which will produce a prototype

  14. GANT chart and development plan Special Thanks to P. Barrillon for the layout.

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