PowerPC SCC port and EC/ECP HDLC controller Communication

1. PowerPC SCC port and EC/ECP HDLC controller Communication SBO, Q2/2005 by James Lee

2. Overview HDLC is the abbreviation for High-Level Data Link Control published by the International Standards Organization (ISO). The HDLC protocol is defined in ISO3309 and related ISO standards. HDLC was the result of an effort by the international community to develop a standard for data link communication. This data link protocol such as LAPB, LAPD, LLC and SDLC are all based on the HDLC protocol with a few modification. Lattice EC/ECP supports the HDLC core for CCITT, CRC16 and CRC32 standard, also supports Embedded block ram for Data queuing.

3. Index • Feature of HDLC controller • Block diagram of HDLC controller • Application of HDLC controller • Tx data modification for accommodation with SCC • Modification Source code • Samsung Design description

4. Features of HDLC controller • Parameterizable number of HDLC channels in multi-channel design. Each channel corresponds to a DS0channel in the TDM & PCM highway. • CRC (Cyclic Redundancy Check) check with parameterizable FCS (Frame Check Sequence) length andarbitrary polynomials. • Flag insertion and detection • Abort generation and detection • Zero insertion and deletion • Idle insertion • Flag sharing between HDLC frames • Recognize 011111101111110 as two continuous flags • Conforms to ISO/IEC 3309

5. R_Shift T_Shift R_Buffer T_Buffer 7 7 7 7 0 0 0 0 R_Control A_Insert T_Control F_INSERT BIT_CNT STATUS F_Detect Z_Unstuff CRC_CHK A_Detect Z_Stuff CRC_GEN 01111110 Block Diagram of HDLC controller EC/ECP Packet Size FIFO Rx HDLC Controller CPU Interface Block Rx Control Logic CPU Line Card Rx_Data Rx HDLC 256x8 Rx FIFO Rx Data Data Rx_Clk 512x8 8bits Add Interrupt Control ( HDLC Tx/Rx controller for CCITT, CRC16, CRC32) CPU_CS Tx HDLC Controller CPU_WRn Register Block CPU_DSn Tx_Clk Tx FIFO CPU_Clk Tx Data CPU_INTn 8bits 512x8 Tx HDLC Tx Control Logic Tx Modification Logic Tx_Data

6. Application of HDLC controller Line Card Processor Card PowerPC SCC Line Card PowerPC SCC EC/ECP/XP HDLC Controller . . . PowerPC . . . Line Card PowerPC SCC Line Card PowerPC SCC SCC (Serial Communications Controllers) HDLC (High-level Data Link Control)

7. HDLC Frame Format

8. 1 F 7 E 7 E Tx Modification for accommodating HDLC format with SCC 1 1 0 0 0 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 5 F 7 E 7 E 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 9 F 7 E 7 E 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 C F 7 E 7 E FCS Flag When the last FCS byte is hx1F, hx9F, hx3F, hxEF, Tx data modulation is needed to avoid abort alarm in PowerPC SCC port

9. 1 1 F F 3 7 F E 7 7 E E 1 1 0 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 FCS Modified Flag Flag Tx Modification for accommodation with SCC 1 1 0 0 0 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 Abort Alarm is occurred in SCC port FCS Flag Flag Whenever there are five consecutive 1’s followed by a zero, the zero will be ignored in PowerPC SCC port. So the zero which is located between FCS and Flag is ignored and SCC port recognized Abort status To avoid Abort status, Modified flag is need

10. Modification source code Process(RST, CLK, Int0_reg) begin if rst = '0' then Int0_reg <= ( others => '0'); elsif CLK'event and CLK = '0' then if (Int0_reg(14 downto 0) = "011111011111100") then Int0_reg(16 downto 0) <= int0_reg(15) & "011111001111110" & txdata0a; else Int0_reg(16 downto 0) <= Int0_reg(15 downto 0) & txdata0a; end if; end if; end process; Txdata0 <= Int0_reg(16);