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A Soda Machine Controller

A Soda Machine Controller. Or, a Pop Machine Controller, depending on where you grew up…. Problem Statement. Design a soda machine controller Soda costs 45 cents Give change in smallest # coins possible. Soda Machine Controller Parts. A coinbox mechanism

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A Soda Machine Controller

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  1. A Soda Machine Controller Or, a Pop Machine Controller, depending on where you grew up… ECEn 224

  2. Problem Statement • Design a soda machine controller • Soda costs 45 cents • Give change in smallest # coins possible ECEn 224

  3. Soda Machine Controller Parts • A coinbox mechanism • Accept coins and signal when they are inserted • Eject coins in response to commands • A dispense mechanism • Dispense a soda in response to a command • A keypad • For accepting input from the user • A display • Some lights for communicating to the user ECEn 224

  4. Step #1: Understand the Complete System Requirements ECEn 224

  5. The Coinbox Mechanism • The VCM7 coinbox • 3 low-asserted outputs: qRec, dRec, nRec • Signal when quarters, dimes, or nickels received • 3 high-asserted inputs: ejQ, ejD, ejN • Tell it to eject a quarter, dime, or nickel +5V VCM7 VendingMachineCoinMechanism qRec ejQ dRec ejD nRec ejN ECEn 224

  6. Electrical Coinbox Considerations • Electrical • VCM7 is 5V part (inputs and outputs) • Our FPGA is 5V tolerant (will accept 5V inputs) • Our FPGA can be configured to output 5V signals on selected pins ECEn 224

  7. Functional Coinbox Considerations We may need answers to a few questions: • Will only one “coin received” signal be asserted at a time? • How long will the “coin received” pulses be? • Is there a guaranteed gap between “coin received” pulses? • Will the VCM7 reject incoming coins when it is ejecting a coin? • How fast can the VCM7 eject coins? • How long must the “coin eject” pulses be? ECEn 224

  8. Functional Coinbox Considerations After a call to the company we get the answers… • Will only one “coin received” signal be asserted at a time?Yes • How long will the “coin received” pulses be?10-12 ms • Is there a guaranteed gap between “coin received” pulses?Yes (2 ms) • Will the VCM7 reject incoming coins when it is ejecting a coin?Yes • How fast can the VCM7 eject coins?500 ms between eject signal pulses • How long must the “coin eject” pulses be?45-50 ms From this, we can draw a timing diagram… ECEn 224

  9. VCM7 Timing Diagram 2ms min Note: coin received signals pulse LOWto indicate receipt of a coin. 10ms min12ms max qRec,dRec,nRec Note: you should pulse eject coin signal HIGHto eject a coin. ejQ, ejD, ejN 45ms min50ms max 500ms min VCM7 will refuse coins during this period ECEn 224

  10. More VCM7 Questions • Is there a way to tell if the VCM7 even has a quarter, dime, or nickel available? • Don’t want to accept coins if you cannot make change… • Is there a way to tell the VCM7 to refuse to accept coins? • After another call to the company, we know the answers: • No and no • But, the VCM8 has these additional features ECEn 224

  11. The VCM8 Coinbox Mechanism +5V ejQ VCM8 VendingMachineCoinMechanism qRec ejD dRec ejN nRec qPres dPres acceptCoin nPres Signal presence of at least onequarter, dime, nickel, … These are high-asserted signals VCM8 will refuse coinsany time this is asserted All other behavior is same as VCM7 ECEn 224

  12. The Dispense Mechanism Step #2: Pulse dispense highDispense takes place on rising edge 5μs min dispense itemNum 0111 Step #1: Place 4-bit address of item to vend on itemNum wires ECEn 224

  13. Dispense Mechanism Considerations • All signals are 5V signals • Need to obey 5 μs setup time ECEn 224

  14. 1 2 3 4 5 6 7 8 9 Coin Return The Keypad c2 c0 c1 r0 r1 r2 cr Buttons 1-9 encoded by row and column wires going high ECEn 224

  15. Keypad Considerations • All signals are 5V signals • Keypad buttons are noisy • Must be debounced • 10 ms max settling time ECEn 224

  16. The Display • The display consists simply of 2 LEDs: • A light to say machine is accepting coins • A light to say enough money has been inserted and a soda can be selected ECEn 224

  17. Step #2: Determine a System Architecture ECEn 224

  18. qRec VCM8CoinMechanism CentralControlSubsystem KeypadInterfaceSubsystem Keypad cr dRec coinReturn nRec btnPushed r0 qPres r1 dPres r2 nPres c0 ejQ c1 c2 ejD ejN acceptCoin itemNum 4 enough On-chip/off chipboundary DispenseMechanism TimerSubsystem clrTimer 5μs vend 46ms 501ms ECEn 224

  19. System Organization Considerations • Central Control Subsystem is FSM controller • A timer is required to time various events • Keypad interface system will: • Debounce keypad buttons • Encode row/col wires into 4-bit number • Tell FSM when one of buttons 1-9 is pushed • Tell FSM when coin return button is pushed ECEn 224

  20. Step #3: Design the Pieces Design the FSM last to reduce number of design iterations ECEn 224

  21. Design of the Timer Subsystem ECEn 224

  22. qRec VCM8CoinMechanism CentralControlSubsystem KeypadInterfaceSubsystem Keypad cr dRec coinReturn nRec btnPushed r0 qPres r1 dPres r2 nPres c0 ejQ c1 c2 ejD ejN acceptCoin itemNum 4 enough On-chip/off chipboundary DispenseMechanism TimerSubsystem clrTimer 5μs vend 46ms 501ms ECEn 224

  23. The Timer Subsystem • Entire system is clocked at 1MHz • Required delays: • 5μ seconds = 5 cycles • 46ms = 46,000 cycles • 501ms = 501,000 cycles • Need a 19-bit counter • Basic system is MUX+Register to select between 0 and count+1 • Just like in switch debouncer design example and Chapter 12 ECEn 224

  24. The =5 Comparator Block – Version #1 count[18:0] = output ”0000000000000000101” This is an inefficient design. It can be done with a 3-input AND gate. ECEn 224

  25. The =5 Comparator Block – Version #2 count[2] count[1] 5 μs count[0] After counter is cleared, it will reach this condition in 5 cycles. ECEn 224

  26. The =46,000 Comparator Block count18-count0 = output ”000 1011 0011 1010 1111” 45,999 Requires 16-input AND Could reduce width of AND gate by choosing some value near 46,000 with lots of low-order 0’s 45,952 (000 1011 0011 1000 0000) – could do with a 9-input AND 46,080 (000 1011 0100 0000 0000) – could do with 6-input AND 47,104 (000 1011 1000 0000 0000) – could do with 5-input AND Do you see why? ECEn 224

  27. The =501,000 Comparator Block • Do something similar to the =46,000 block just seen OR • Final carry-out of +1 circuit is =219 signal (=524,288) • We can eliminate the 19-bit AND • Could play similar trick with =46,000 if happy with powers-of-2 • Bit 16 corresponds to 216 = 65,536 • 65.536 ms is longer than the 50 ms maximum allowed ECEn 224

  28. Detecting 219 Use this signal for 219 S18 S1 S0 … HalfAdder HalfAdder HalfAdder C19 C2 C1 C0 ‘1’ A18 A1 A0 ECEn 224

  29. Design of the Keypad Interface Subsystem ECEn 224

  30. qRec VCM8CoinMechanism CentralControlSubsystem KeypadInterfaceSubsystem Keypad cr dRec coinReturn nRec btnPushed r0 qPres r1 dPres r2 nPres c0 ejQ c1 c2 ejD ejN acceptCoin itemNum 4 enough On-chip/off chipboundary DispenseMechanism TimerSubsystem clrTimer 5μs vend 46ms 501ms ECEn 224

  31. Keypad Interface Functions • Debounce the 7 inputs from keypad • Determine when button has been pressed and assert btnPressed signal • Encode button number on itemNum signal bits ECEn 224

  32. Keypad Interface Block Diagram coinReturn cr debounce 10ms Detect and Encode r0 debounce 10ms r1 debounce 10ms r2 debounce 10ms btnPressed c0 debounce 10ms c1 debounce 10ms c2 debounce 10ms 4 itemNum ECEn 224

  33. The Keypad Detect and Encode Block • Easiest way to implement is as lookup table • Use a ROM • Encode not only itemNum but also btnPressed • Easy to reject illegal combinations • 2 buttons pressed, column asserted but not row, etc. • Output should be loaded into register, so choice is remembered … ECEn 224

  34. r2 r2 r2 r2 c0 c0 c0 c0 c1 c1 c1 c1 c2 c2 c2 c2 2 CombLogic CombLogic CombLogic CombLogic Detect and Encode Using 4LUTs Only Truth Table 4LUT 00xxxx x x x x x 00xxxx x x x x x … 00xxxx x x x x x 01xxxx x x x x x 01xxxx x x x x x … 01xxxx x x x x x 10xxxx x x x x x 10xxxx x x x x x … 10xxxx x x x x x 11xxxx x x x x x 11xxxx x x x x x … 11xxxx x x x x x 4LUT 4LUT 00 01 10 11 i3 4LUT r0r1 4LUT Very similar to decomposition when we used MUX blocksto implement truth tables… ECEn 224

  35. Design of the Central Control Subsystem ECEn 224

  36. qRec VCM8CoinMechanism CentralControlSubsystem KeypadInterfaceSubsystem Keypad cr dRec coinReturn nRec btnPushed r0 qPres r1 dPres r2 nPres c0 ejQ c1 c2 ejD ejN acceptCoin itemNum 4 enough On-chip/off chipboundary DispenseMechanism TimerSubsystem clrTimer 5μs vend 46ms 501ms ECEn 224

  37. 3 3 3 3 add25 add10 sub10 sub25 sub45 enough gte10 gte25 add5 sub5 clrAccum gt0 FSM + Accumulator FSM qRec, dRec, nRec globalReset qPres, dPres, nPres coinReturn acceptCoin btnPushed clrTimer 5μs vend 46ms 501ms enough Accumulator ECEn 224

  38. Accumulator Functions • Totals money as inserted • Inform FSM of balance • Enough to buy a soda • At least 25 cents • At least 10 cents • At least 5 cents • All money in terms of 5 cent increments • Count in 5 cent increments instead of cents ECEn 224

  39. Accumulator Block Diagram FSM tells it toadd money,subtract money,or clear add5,add10,add25 accumValue ClearableAccumulator IFL 4 sub5,sub10,sub25 accum 4 clr sub45 addSub# clrAccum load It tells FSMhow much moneyit has totalled clk gt0 OFL gte10 gte25 enough We are going to build it in the MUX+Register styleof Chapter 12 ECEn 224

  40. D Q The Clearable Accumulator Sub-Block 0 1 accum 4 4 add/sub 4 accumValue 4 0 1 4 4 0 addSub# load clk clr ECEn 224

  41. D Q The Clearable Accumulator Sub-Block 0 1 accum 4 4 add/sub 4 accumValue 4 0 1 4 4 0 addSub# load clk clr Loadable register ECEn 224

  42. D Q The Clearable Accumulator Sub-Block 0 1 accum 4 4 add/sub 4 accumValue 4 0 1 4 4 0 addSub# load clk clr Clear capability ECEn 224

  43. D Q The Clearable Accumulator Sub-Block 0 1 accum 4 4 add/sub 4 accumValue 4 0 1 4 4 0 addSub# load clk clr Add/sub capability ECEn 224

  44. D Q The Clearable Accumulator Sub-Block 0 1 accum 4 4 add/sub 4 accumValue 4 0 1 4 4 0 addSub# load clk clr What has priority? addSub#, clr, or load? ECEn 224

  45. Building an Adder S3 S2 S1 S0 … C4 C3 C2 C1 Full Adder Full Adder Full Adder Full Adder C0 = 0 B3’ B2’ B1’ B0’ A3 B3 A2 B2 A1 B1 A0 B0 ECEn 224

  46. Building a Subtractor S3 S2 S1 S0 … C4 C3 C2 C1 Full Adder Full Adder Full Adder Full Adder C0 = 1 B3’ B2’ B1’ B0’ Add 1 Invert B A3 B3 A2 B2 A1 B1 A0 B0 In chapter 8 we learned about how to use an adder asa subtractor: invert B and add 1 ( A-B = A + (-B) ) ECEn 224

  47. Building an Adder/Subtractor S3 S2 S1 S0 … C4 C3 C2 C1 Full Adder Full Adder Full Adder Full Adder sub B3’ B2’ B1’ B0’ 0 1 0 1 0 1 0 1 sub sub sub sub A3 B3 A2 B2 A1 B1 A0 B0 Here is a design that either adds or subtracts (Either inverts B and adds 1 or doesn’t) ECEn 224

  48. 0 1 Simplified Adder/Subtractor q q sub b sub b If you don’t believe it, do a truth table… ECEn 224

  49. Final Adder/Subtractor S2 S1 S0 FullAdder FullAdder FullAdder … C2 C1 C0 addSub# A2 A1 A0 B2 B1 B0 ECEn 224

  50. Accumulator IFL Block • Use these signals: add5, add10, add25, sub5, sub10, sub25, sub45, clrAccum • Generate these signals: accumValue[3:0], clr, addSub#, load • There are many ways to do this • Not unlike there being many ways to write any particular computer program • We will show an intuitive approach rather than a truth-table approach ECEn 224

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