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Test and Monitor with the CIBT

Learn about the CIBT's role in the LHC Beam Interlock System, including its functions as a serialiser/deserialiser and a display driver. Explore the testing and monitoring capabilities, as well as the implementation details of the system.

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Test and Monitor with the CIBT

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  1. Test and Monitor with the CIBT 1. CIBT Overview • Location • SPS vs LHC Chassis 2. CIBT Realisation • Serialiser / Deserialiser • BEAM_PERMIT_INFO • CIBTD Display Driver • Remarks LHC Beam Interlock System

  2. Overview • CIBT linked to each CIBM • TESTing CIBU • MONITORing CIBU • Drives Beam Permit Info • For some CIBU LHC Beam Interlock System

  3. Overview LHC Type Chassis SPS Type Chassis LHC Beam Interlock System

  4. Principle Function CIBT primarily acts as a SERialiser DESerilaiser (SERDES), Or.. A fancy MUX / DEMUX of serially encoded signals ‘hot’ redundancy! LHC Beam Interlock System

  5. TEST and MONITOR Simple signal paths -automatically swaps between broken links inside the controller -appends internal status of the CIBT LHC Beam Interlock System

  6. Implementation It has two other functions.. -Drive BEAM_PERMIT_INFO -Illuminate a small Display Display driver is carried out independantly! Implemented in Spartan 2 FPGAs 5V compatible I/O LHC Beam Interlock System

  7. BEAM_PERMIT_INFO Simple circuits, a pair of majority voters… -Extra pins were available, used to increase availability ZT ZT ZT LHC Beam Interlock System

  8. BEAM_PERMIT_INFO LHC Simple circuits, a pair of majority voters… -B1 versus B2 Circuits exploit RS485 multidrop: LHC Beam Interlock System

  9. BEAM_PERMIT_INFO SPS Simple circuits, a pair of majority voters… -LEFT & RIGHT Circuits exploit RS485 multidrop: LHC Beam Interlock System

  10. Display CIBTD Simple display, short circuit can risk only the display FPGA LHC Beam Interlock System

  11. Functions Explained • TESTING • CIBM writes a buffer to the CIBT, serialised comms, not VME • CIBT transmits this information to the CIBU devices twice per second • MONITORING • CIBT writes a buffer to the CIBM, serialised comms, not VME • CIBT writes around 16 bits which represent internal state • CIBM transmits this combined information to the CIBM twice per second • N.B. increasing the rate to 1k or thereabouts is planned (DC balancing) • BEAM_PERMIT_INFO • CIBT receives two sets of BPI signals, each in TMR • -if either is TRUE, it sets the internal BPI to TRUE • RS485 multidrop is used to accommodate all the configurations • CIBTD • The data sent back to the CIBM is sent in parallel to the CIBTD • LEDs illumate corresponding to data • Simple board, not critical if it fails! LHC Beam Interlock System

  12. FIN LHC Beam Interlock System

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