A FAULT MODEL OF INPUT-OUTPUT PIN PAIRS AND TRIPLETS

1. A FAULT MODEL OF INPUT-OUTPUT PIN PAIRS AND TRIPLETS R. Šeinauskas Kaunas University of Technology LITHUANIA MIXDES”04, Szczecin

2. Topics • INTRODUCTION • A PIN PAIRS FAULT MODEL • A PIN TRIPLETS FAULT MODEL • THE EXPERIMENTS • CONCLUSIONS

3. INTRODUCTION • The stuck-at fault model is well adapted to the circuits on gate level of abstraction. • However, this fault model is not applicable at high abstraction levels of circuit description (RT, functional, behavioural, algorithmic). • Many fault models have been suggested at high abstraction level.

4. INTRODUCTION • Actually all of them are based on perturbations of the description, leaving alone the closeness of the suggested fault model to the real defects of the circuit. • Sometimes they consider very large numbers of perturbations of the description.

5. INTRODUCTION • So far, there are no popular fault models at high abstraction level that could insure proper testing of physical defects of a circuit. • We suggest on high level of abstraction a pin pair and pin triplets fault model that relies on the input-output signals of the whole circuit only.

6. The Pin Pair fault model • Let the circuit have a set of inputs X= {x1, x2, ... ,xi, ... ,xn} and a set of outputs Y = {y1, y2, ... ,yj, ... ,ym}. • The pin fault model considers the stuck-at-0/1 faults occurring at the module boundary • Input-output pin stuck-at fault pairs (xit, zjk), t=0,1, k=0,1 are called pin pair faults (PP).

7. Testing of the PP fault • The test vector detects the pin pair fault (xit, zjk) of the module if the test vector detects both the pin faults xit, and zjk of the pair on the output zj of the module. • The PP fault (xit, zjk) of a module is testable if a conventional deterministic test generator for a realization of the module finds a test vector, which detects a pin fault xit on an output zj while the input xi and the output zj are set up to the ¬t and

8. Circuits Stuck-at Faults Test size PP Faults Test size C432 507 63 540 122 C499 750 63 5184 1053 C880 942 54 1326 379 C1355 1566 92 5184 1023 C1908 1862 123 3004 620 C2670 1990 113 3320 461 C3540 3126 172 2588 513 C5315 5248 130 10540 1113 C6288 7638 34 3068 246 C7552 7039 209 12188 1681 Faults and Test Sets

9. Number of Faults

10. Test Size

11. Circuit Undetected of R1 Undetected of R2 Undetected of R3 C432 11 (2,2%) 6 (1,4)% 3 (0,7%) C499 0 0 0 C880 0 0 0 C1355 0 0 1 C1908 64 (3,4%) 9 (1.0%) 9 (0,7%) C2670 8 (0,4%) 7 (0,5%) 6 (0,4%) C3540 35 (1,1%) 25 (1,0%) 30 (1,2%) C5315 0 0 0 C6288 0 0 0 C7552 25 (0,4%) 8 (0,2%) 4 (0,1%) Total 143 (0,5%) 55 (0,2%) 53 (0,2%) Stuck-at Fault Coverage R1 – The non-redundant ISCAS’85 benchmark circuit R2 – Synopsys Design Optimization , the target library – class.db R3 - Synopsys Design Optimization, the target library – and_or.db

12. Circuits Connectivity Faults Deterministic tests Random+deterministic tests Detected Percent Detected Percent C432 540 406 75,13 467 86,48 C499 5184 1510 29,13 1434 27,66 C880 1326 837 63,12 862 65,01 C1355 5184 2718 52,43 2638 50,89 C1908 3004 1521 50,63 1740 57,92 C2670 3320 2204 66,38 2142 64,51 C3540 2588 2051 79,31 2036 78,73 C5315 10540 7148 67,88 7305 69,30 C6288 3068 2353 76,74 2393 77,99 C7552 Total 45016 20748 59,69 21017 60,47 PP Fault Coverage

13. The input-input-output pin triplet fault model • The PP fault model requires the path sensitisation between an input and an output at least one time. The sensitisation of the paths pair would increase the rate of the separate paths sensitisation. The pin triplets contain such a property. • The input-input-output pin stuck-at fault triplets (xit, yhp, zjk), t=0,1, k=0,1 p=0,1 are called the pin triplets faults (PT).

14. Testing of PT faults • We denote the set of the pin triplet’s faults by • P1= { (xit, yhp, zjk) | i =1,…,n, h=1, ,n, j=1,…,m, t = 0,1, k=0,1 p=0,1}. • The test vector detects the pin triplet fault (xit, yhp, zjk) of the module if the test vector detects the pin faults xit, yhp and zjk of the triplet on the output zj of the module.

15. Circuit Test size PT faults UnR1 NTR1 UnR2 NTR2 UnR3 NTR3 C432 1123 15254 0 77 0 67 0 69 C499 3410 412736 0 65 0 91 0 103 C880 4954 55280 0 73 0 49 0 53 C1355 3356 412736 0 105 0 109 0 109 C1908 2505 154284 7 (0,38%) 163 3 (0,34%) 94 3 (0,25%) 124 C2670 3259 187270 0 173 0 161 0 165 C3540 7022 123332 0 188 0 144 1 (0,04%) 149 C5315 4679 269726 0 207 0 175 0 174 C6288 2178 152802 0 59 0 73 0 72 C7552 14310 805932 6 (0,09%) 346 1 (0,02%) 266 0 238 Total 46796 2589352 13 1456 4 1229 4 1256 The test size and the undetected stuck-at faults for three realizations NTRi – The number of the test patterns selected by a fault simulation for the realization Ri UnRi – The number of the undetected stuck-at faults for the realization Ri

16. Detectable PT faults • We see that the test sets for the input-input-output pin stuck-at fault triplets almost covers stuck-at faults for all three realizations, but the size of test sets and the number of detectable PT faults is huge. • The necessary test pattern for each realization can be selected from the generated test sets by a fault simulation

17. Circuit Test sets generated for stuck-at faults Test sets selected from PT fault test R1 R2 R3 R1 R2 R3 C432 57 46 45 77 67 69 C499 54 74 80 65 91 103 C880 62 49 50 73 49 53 C1355 86 83 80 105 109 109 C1908 118 57 75 163 94 124 C2670 105 120 116 173 161 165 C3540 167 143 147 188 144 149 C5315 130 99 89 207 175 174 C6288 43 47 34 59 73 72 C7552 211 146 138 346 266 238 Total 1033 864 854 1456 1229 1256 The length of test sets

18. Test generation • Test vectors for PP and PT faults can be generated by conventional deterministic test generator if a circuit model is suitable for test generation • The number of PP and PT faults is 4*n*m and 4*n*n*m. A lot of PP and PT faults are undetectable. The proof by test generator that the fault is undetectable is time consuming. • Random search is applicable if the circuit model is suitable only for simulation

19. The random search termination conditions • One of various feasible termination condions may be the probability that defines a possibility to find the input pattern that detects a new black box fault. This probability p=S/N may be expressed by the ratio of the selected input patterns S with the number N of all analyzed input patterns.

20. The last selected input pattern • As a rule the main number of input patterns are selected at the beginning of the random search and when the selection of input patterns that detect all black box faults is over, new input patterns are no longer selected. Therefore an important factor that demonstrates the completeness of the black box faults testing is the ratio r1=N/L, where N is the number of all analyzed input patterns and L is the number of the last selected input pattern. For example, the ratio r1=10 shows that there were generated 9 times more input patterns after the last selected input pattern and that these patterns didn’t detect any new black box faults.

21. Repeated random search • Another important factor demonstrating if all black box faults are being detected is the comparison of the black box faults detected during several independent random search. If the random search of the input patterns was sufficient for selecting the patterns that detect all black box faults, than the input patterns selected during several test generations will detect the same black box faults. Assume that from ten independent test generations the input patterns selected by all ten generations detect the same black box faults, and this is a serious assertion that all black box faults are being checked. The number of such situations we will mark as r2.

22. Circuit Exper N average L average Test size p Average r1 r2 PP faults c432 5 706000 3739 70 0,0001 188,82 5 540 c499 5 5052000 73325 505 0,0001 68,90 5 5184 c880 5 1852000 103242 185 0,0001 17,94 5 1326 c1355 5 4952000 61635 495 0,0001 80,34 5 5184 c1908 5 3230000 94943 323 0,0001 34,02 5 3004 c2670 5 1928000 1871528 192 0,0001 1,03 1 3164 1 54263240 10852648 223 0,000004 5,00 1 3320 c3540 5 2494000 210280 249 0,0001 11,86 5 2588 c5315 5 5726000 154308 572 0,0001 37,11 5 10540 c6288 5 1190000 214112 119 0,0001 5,56 5 3068 c7552 6 7211666 7043246 721 0,0001 1,02 1 9846 1 161024857 157526039 844 0,000005 1,02 1 12188

23. Circuit Number of test generations N average L average Average test size p Average r1 r2 Max number of detected PT faults c432 5 131660 26332 1124 0,008537 5,00 5 15254 c499 5 226640 45328 3392 0,014966 5,00 5 412736 c880 1 100000000 47290644 4904 0,000049 2,11 1 55280 c1355 5 250705 50141 3385 0,013502 5,00 5 412736 c1908 5 18030255 3606051 2535 0,000141 5,00 5 154284 c2670 1 100000000 99337376 2849 0,000028 1,01 1 182366 1 205511 3259 1 187270 c3540 1 100000000 81215067 7018 0,000070 1,23 1 123322 1 197128 7022 1 123332 c5315 1 100000000 7550266 4673 0,000047 13,24 1 269726 c6288 1 100000000 99531738 2140 0,000021 1,00 1 152678 1 69632 2176 1 152802 c7552 1 100000000 99807091 8869 0,000089 1,00 1 548563 1 1103223 12880 1 805932

24. Conclusions • The design for the test and the test generation on system-level model reduces time-to-market. • The test generation on the system-level model can not guarantee a complete fault coverage on the gate-level model for each possible implementation

25. Conclusions • The experiments show that the test sets generated for black-box faults at system level detect in average more than 99 percent of the stuck-at faults of the three different circuit realizations at gate level. • The random search termination • condition determines the • accuracy of the obtained • solution