1 / 17

THE TIMING

Explore the strategic considerations for efficient ASIC design, including pad sizes/pitches, trimmers usage, voltage regulators, sensor placement, and DAC configurations. Discover the impact of sensor geometry and thickness on time resolution with UFSD detectors. Benefits include enhanced electronics contribution and improved time resolution. Collaborate on projects involving FAST readouts and HPTDC preamplifier characterization to advance research and development in VLSI ASIC design. Ensure confidentiality and utilize CAD licenses for comprehensive development.

eddies
Download Presentation

THE TIMING

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. THE TIMING Turin VFE-UFSD Bulletin 19th June 2019 PCB, Simulations, licences T32 VLSI ASIC designers: JonhatanOlaveolave@to.infn.it Federico Faustifausti@to.infn.it

  2. Geometricaldetails • ASIC size: 5 mm x 1.5 mm • pad size: L = 76.5 um; W = 63 um • pad pitch: 90 um • Input pitch: 180 um • bottom pad number: 47 (20 inputs); • top pad number: 51 (40 outputs); • lateral pad number: Sx = 21; Dx = 21 • Total pad number: 140 • FAST: 3 flavors, same pinout  shared PCB

  3. FAST Motherboard OUTPUTS Top levelscheme 50 polesflatconnector shield 3.3 V Bias network How manytrimmers do wereallyneed? Tunable? Voltage regulator FAST x3 1.2 A 1.2 DIG 2.5 IO LM95071 TEMP SENSOR TEST AREA AD5391BSTZ • - Vth • Biaspreamp • What else? DAC CAP TEST SENSOR AREA 1 cm x 1.5 cm TEST PULSE (SMA) HV (SHV) Multiple PIN connector From FPGA/ARDUINO

  4. PCB for FAST: INPUT PADs

  5. PCB for FAST: INPUT PADs SETUP 1: Direct connection

  6. PCB for FAST: INPUT PADs

  7. PCB for FAST: the ABACUS boardlesson • Too many trimmers • Sensor too far from the ASIC (12 mm) • Exaggeratedcompactness hard smdreplacement • No shield for sensro-ASIC • LTC2604 DAC (16 bit)  limited bandwidth • After production voltage divider for DC levels adaption in FPGA-DAC data exchange • LM95071  SPI bus interface; already implemented in Turin projects. • temperature accuracy 0 to 70 °C 1 °C or -40 to 150 °C 2 °C • Temperature resolution 0.03125 °C

  8. PCB and readoutdevelopments • MoVeIT: new PCB for multiple ASIC setup • ABACUS run 2 • FAST readout: collaboration with Milano Bicocca (FPGA in TDC) • Turin INFN + HPTDC

  9. Preamplifiercharacterization

  10. Preamplifiercharacterization MPV

  11. Preamplifiercharacterization Cdet = 6 pF; Qin = trapezoidal; Ibias = 1mA; T = 27 °C; Regular Rf = 20 K; EVO Rf = 11.6 K

  12. Time resolution with UFSD detectors • Study done playing with three important parameters: • Sensor thickness: 35 um, 55 um, 75 um • Sensor geometry: 1x1 mm2, 1.3x1.3 mm2 and 1x3 mm2 • FAST flavors: REGULAR, EVO1 and EVO2 Sensor contribution Electronics contribution + + + +

  13. Time resolution with UFSD detectors CONFIDENTIAL

  14. Time resolution with irradiatedsensors http://personalpages.to.infn.it/~cartigli/Weightfield2/Library.html

  15. Time resolution with irradiatedsensors Irradiation [neq/cm2]

  16. Example of run @ 3°15neq/cm2 7263 events EVO1

  17. CAD Licenses

More Related