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SEQUENTIAL LOGIC

SEQUENTIAL LOGIC. Sequential Logic. Positive Feedback: Bi-Stability. Meta-Stability. Gain should be larger than 1 in the transition region. R. S. Q. Q. S. 0. Q. 0. Q. S. Q. 0. 0. 1. 1. Q. R. 0. 1. 0. 1. R. 1. 0. 1. 0. S. Q. Q. R. SR-Flip Flop. Q. Q. R. S. Q.

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SEQUENTIAL LOGIC

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  1. SEQUENTIAL LOGIC

  2. Sequential Logic

  3. Positive Feedback: Bi-Stability

  4. Meta-Stability Gain should be larger than 1 in the transition region

  5. R S Q Q S 0 Q 0 Q S Q 0 0 1 1 Q R 0 1 0 1 R 1 0 1 0 S Q Q R SR-Flip Flop Q Q R S Q Q S Q 1 Q 1 Q Q R 0 1 1 0 1 0 0 1 0 1 0 1

  6. JK- Flip Flop

  7. Other Flip-Flops

  8. Race Problem

  9. Master-Slave Flip-Flop

  10. Propagation Delay Based Edge-Triggered

  11. Edge Triggered Flip-Flop

  12. Flip-Flop: Timing Definitions

  13. Maximum Clock Frequency

  14. CMOS Clocked SR- FlipFlop

  15. Flip-Flop: Transistor Sizing

  16. 6 Transistor CMOS SR-Flip Flop

  17. Charge-Based Storage

  18. Master-Slave Flip-Flop

  19. 2 phase non-overlapping clocks

  20. 2-phase dynamic flip-flop

  21. Flip-flop insensitive to clock overlap

  22. C2MOS avoids Race Conditions

  23. Pipelining

  24. Pipelined Logic using C2MOS

  25. Example

  26. NORA CMOS Modules

  27. Doubled C2MOS Latches

  28. TSPC - True Single Phase Clock Logic

  29. Master-Slave Flip-flops

  30. Schmitt Trigger • VTC with hysteresis • Restores signal slopes

  31. Noise Suppression usingSchmitt Trigger

  32. CMOS Schmitt Trigger Moves switching threshold of first inverter

  33. Schmitt TriggerSimulated VTC

  34. CMOS Schmitt Trigger (2)

  35. Multivibrator Circuits

  36. Transition-Triggered Monostable

  37. Monostable Trigger (RC-based)

  38. Astable Multivibrators (Oscillators)

  39. Voltage Controller Oscillator (VCO)

  40. Relaxation Oscillator

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