VHDL: The Very Basics

1. VHDL: The Very Basics CprE 488x

2. VHDL • VHDL: VHSIC Hardware Description Language (VHSIC → Very High Speed Integrated Circuit) • VHDL is widely used to model digital systems. • Used as a design verification and validation tool.

3. VHDL Code Structure • Entity Declaration • Defines input/output ports • Architecture Declaration • Defines what the component does • Variables, Signals, Constants defined • Component Mapping • Interconnects previously defined components/entities.

4. Overview • Entity Declaration • Declare the signals that come in and out of your component. • Architecture Declaration • Perform the internal functionality of your module.

5. VHDL Code of Previous Block2-Bit Adder

6. VHDL Structure • Entity Declaration • Specifies the unit’s ports • States the port’s name, type and length • Input/Output/Inout • Length varies from single bit to vectors

7. VHDL Structure • Entity Declaration • Specifies the unit’s ports • States the port’s name, type and length • Input/Output/Inout • Length varies from single bit to vectors

8. VHDL Structure • Architecture Declaration • Describes the operation of an entity • Declares all signals and components used • Process Sensitivity List • Contains all the ports to which the process is sensitive • Used to indicate which signal change triggers a process revision

9. VHDL Structure • Process Sensitivity List • Contains all the ports to which the process is sensitive • Used to indicate which signal change triggers a process revision

10. Component Instantiation • Reuse the 2-bit adder to create a 4-bit adder. • New Entity with: • A and B as two input bit vectors. • Cin as a single bit input. • C as an output bit vector. • Cout as a single bit output. • The architecture of the 4-bit adder is compose of 2 calls to the 2-bit adder.

11. Component Instantiation • Declaration • component name • Port( • Signal name : type • ); • end component • Instantiation • instantName : ComponentName • port map( • internalSignal => externalSignal • );

12. Component Instantiation

13. State Machine ExampleJust for fun!

14. Questions???? rmercado@iastate.edu