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Real Time Correlator in FPGA

Real Time Correlator in FPGA. Xu ZhiJun, Zhang XiuZhong Shanghai Astronomical Observatory China 4 th IVS General Meeting January 9, 2006. OUTLINE. Main Characteristics Architecture of the Correlator FFT & MAC Board Some results Future Plan. Main Characteristics.

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Real Time Correlator in FPGA

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  1. Real Time Correlator in FPGA Xu ZhiJun, Zhang XiuZhong Shanghai Astronomical Observatory China 4th IVS General Meeting January 9, 2006

  2. OUTLINE • Main Characteristics • Architecture of the Correlator • FFT & MAC Board • Some results • Future Plan

  3. Main Characteristics • 3 Stations FX Correlator ( 5 stations, 8 IFs ) • date rate：0 - 32M samples/s, 1 or 2 bits/sample • Integration Time：32.768 millisecond – 1 hour (typical 5s) • Input data format: MKIV, MKV or others( VSI, VLBI) • data source ：Disk Array, Network • Output: via net and disk files ( in FITS format) • Fringe searcher, Phase Cal ( in Hardware)

  4. Architecture of Correlator

  5. LTA Monitor (real time fringe display) PBI (xc2v3000) PBD FFT & MAC (xc4vsx35) CCC LTA MOXA Card

  6. FFT & MAC Board Diagram 32M 160M 32M CLKPBI_1 D E L A Y F R I N G E FFT 16bits Scaled Fixed Point F S T C M A C Data Output LTA 7300A PBI_1 DATA CLKPBI_2 16bits PBI_2 DATA CLKPBI_3 8M PBI_3 DATA Model Input 4M MCC

  7. Model Input - Time Diagram Period of 6 coefficient polynomial = 1min CLK_4M RESET 160x1024 bits （linear model period） READY_PARA CLK_PARA 192x3 bits 192x3 bits 192x3 bits PARASTR

  8. Integer Bit Delay C1 CLKPBI_1 C2 CLKPBI_2 C3 CLKPBI_3 CLKFRINGE C1=6 C2=4 C3= -3

  9. Fringe Stopping i= 1, 2 …, linear Model period (160x1024 bits) 14bits Unsigned Sine-Cosine Look-Up Table Xilinx IP Core PING-PANG RAM 1(b) 2(b) 3(b) 16bits 1(a) RAM 16x2 x1024 2(a) RAM 16x2 x1024 3(a) RAM 16x2 x1024 Sine Cosine Complex Multiply 3x2x16 bits 16bits ‘1’ = x“4000” ‘0’ = x”C000” PBI-1 PBI-2 PBI-3

  10. FFT(Fast Fourier Transform) Done PING-PANG RAM Xilinx IP Core 1(b) 2(b) 3(b) 9 bits FFT 16 bits 1024 Fixed Point F S T C Index 1(a) RAM 16x2 x1024 2(a) RAM 16x2 x1024 3(a) RAM 16x2 x1024 Address FFT_R 10 bits 16 bits FFT_I 1 2 3 DATA_R DATA_I (16 bits)

  11. FSTC(Fractional Sample Time Correction) τ = d + e(f-1) f= 1, 2 …,FFT num per linear Model period (160) FSTC = i* τ/ N i=1, 2 … , N/2 N is FFT point PING-PANG RAM 14bits Unsigned 1(b) 2(b) 5(b) Sine-Cosine Look-Up Table 1(a) RAM 16x2x512 2(a) RAM 16x2x512 5(a) RAM 16x2x512 Xilinx IP Core 16bits Sign Sine Cosine FFT_R 1 2 3 DATA_R DATA_I (16 bits) 16 bits DATA_R = FFT_R * Cosine - FFT_ I * Sine DATA_ I = FFT_ I * Cosine + FFT_R * Sine FFT_I

  12. MAC(multiple and accumulate) 42x2 bits X_R X_I 16 bits 1~1023次 R RAM 42x512 I RAM 42x512 Dout_R Dout_I 42x2 bits 42x2 bits 16 bits Acc RAM Y_R Y_I 1024次 R RAM 42x512 I RAM 42x512 DOUT_R = X_R * Y_R + X_I * Y_I DOUT_ I = X_I * Y_R - X_R * Y_I Output RAM

  13. FFT & MAC Board ML402 Evaluation Platform (V4-SX35)

  14. FPGA Chip Usage • xc2v3000 Number of MULT18X18s 37 out of 96 38% Number of RAMB16s 86 out of 96 89% Number of SLICEs 7301 out of 14336 50% • xc4vsx35 Number of DSP48s 43 out of 192 22% Number of RAMB16s 76 out of 192 39% Number of Slices 6056 out of 15360 39%

  15. Results – Simulation data Station 1 - Station 2 Station 1 - Station 3 Station 2 - Station 3

  16. Results – TC-1 Satellite The Fringe of the SH-UR Baseline TC-1 observation with Integration time of 62.5 ms

  17. Results – TC-1 Satellite (cont.) The Fringe of the SH-UR Baseline TC-1 observation with Integration time of 4 seconds

  18. Future Plan • 5 stations, 8 IFs • Network creation • System auto-operation software development • Hardware Fringe searcher, Phase Cal

  19. Thank you 

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