Combinational Design, Part 3

1. Combinational Design,Part 3 Chapter 4 (Sections 3, 4, 5)

2. Topics • Common Logic Functions • Decoders • Encoders • Multiplexers

3. Value Fixing, Transferring, Inverting • Only 4 possible functions of one variable • 2 constant • 1 xfer • 1 invert

4. Enable • Enable is a common input to logic functions • See it in memories, and today’s blocks

5. Decoders • Discrete quantities are represented by binary codes. • n-bit binary code is capable of representing 2n distinct elements of coded information. • Decoding is the conversion of an n-bit code to an m-bit output code with n<= m <= 2nsuch that each valid input code produces a unique output code. • Decoding is performed by a decoder. • The decoder may have unused bit combinations on its inputs for which no corresponding m-bit code appear on the output

6. 1-to-2 Line Decoder Decoders • Typically n inputs and 2n outputs • The purpose is to generate 2n or fewer minterms. • Drives high the output corresponding to binary code of input

7. Note that the 2-to-4 decoder is made of 2 (1-to-2 ) line decoders and 4 AND gates 2-to-4 Line Decoder

8. 2-to-4 Decoder with Enable

9. Truth Table, 3-to-8 Decoder • Notice they are minterms

10. Schematic 8 3-inputAND gates are needed

11. Alternative Design: Multi-Level 3-to-8 Level 1 1-to-2 Line decoder Level 2 Build 2-to-4 Line decoder using level 1 decoders with 4 2-input AND gates Level 3: Build 3-to-8 Line decoder using level 1, level 2 decoders with 8 2-input AND gates

12. Enable Used for Expansion

13. …. = C0B0 B0, B1, B2, …, B7 D7= C0B7 … D8= C1B0 D15= C1B7 C0, C1, C2, …, C7 = C7B7 Multi-Level 6-to-64 Decoder …. ...

14. Uses for Decoders • Binary number might serve to select some operation • Computer operation codes are encoded • Decoder lines might select add operation, or subtract operation, or multiply operation, etc. • Memory address lines

15. Variations • At right • Enable not • Inverted outputs

16. 74139 74139Two 2-to-4 Line Decoders; Enable Not ; Inverted Outputs

17. Encoder • Encoder is the opposite of decoder • 2n inputs • or less – 10 inputs in BCD: I0, I1, I2, I3, …, I9 • n outputs • 4 output line for BCD code

18. Truth Table

19. Inputs are Minterms • Can OR them together appropriately • A0 = D1 + D3 + D5 + D7 • A1= D2 + D3 + D6 + D7 • A2= D4 + D5 + D6 + D7

20. What’s the Problem? • What if D3 and D6 both high? • Simple OR circuit will set A (the output) to 7

21. Priority Encoder • Chooses one with highest priority • i.e. produce the code of the input with the highest priority • Largest number, usually • Note “don’t cares” What if all inputs are zero?

22. Need Another Output • A “Valid” output

23. Figure 4-12 Logic Diagram of a 4-Input Priority Encoder Valid is OR of inputs

24. K Map for A0 • X on an input means the circuit must generate the specified output value for both input possibilities: 0, 1

25. 74153 Multiplexer (or Mux) • Selects one of a set of inputs to pass on to output • Binary control code, n lines • Choose from 2n inputs • Useful for choosing from sets of data • Memory or register to ALU • Very common

26. Two Input Mux

27. 4-to-1-Line Multiplexer Logic: Four Input Mux

28. A Single Bit 4-to-1 Line Multiplexer Logic is a Decoder Plus4 X 2-Input AND gates feeding an OR gate

29. Quad 2-to-1 Mux • Select one of two sets of lines A & B; each set has 4 lines • Practical use: Select a whole 64-bit data bus from one of many sources

30. Gate input count is 18 Three-State Implementation

31. Gate input count is 14 Binary Tree Style

32. 1-to-4-Line Demultiplexer Demultiplexer • Takes one input • Out to one of 2n possible outputs

33. Demux is a Decoder • With an enable

34. A Demux Using NAND Gates:A Decoder with an Enable