1 / 52

Combinational Design, Part 3: Functional Blocks

Combinational Design, Part 3: Functional Blocks. Chapter 3 (Sections 6, 7, 8, 9). Topics. Rudimentary Logic Functions: Value fixing, Transferring, and Inverting Common Logic Functions Decoders Encoders Multiplexers. Table 3-3. Value Fixing, Transferring, Inverting.

gaylam
Download Presentation

Combinational Design, Part 3: Functional Blocks

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Combinational Design,Part 3: Functional Blocks Chapter 3 (Sections 6, 7, 8, 9)

  2. Topics • Rudimentary Logic Functions: Value fixing, Transferring, and Inverting • Common Logic Functions • Decoders • Encoders • Multiplexers

  3. Table 3-3 Value Fixing, Transferring, Inverting • 4 possible functions of one variable • constants (0,1) • Transfer • Invert

  4. Enable • Enable is a common input to logic functions • See it in memories, and logic building blocks Which we will Discuss next

  5. 1-to-2 Line Decoder Decoders • Typically n inputs and 2n outputs • The output line corresponding to the input code is high

  6. Decoder Examples = = = • Note that the 2-4-line made up of 2 1-to-2- line decoders and 4 AND gates. = • 2-to-4-Line Decoder A 0 A A D D D D 1 0 0 1 2 3 A 1 0 0 1 0 0 0 D A A 0 1 0 0 1 0 1 0 0 1 0 0 0 1 0 D A A 1 1 0 0 0 1 1 1 0 (a) D A A 2 1 0 D A A 3 1 0 (b)

  7. 2-to-4 Decoder with Enable

  8. Truth Table, 3-to-8 Decoder • Notice the outputs are minterms

  9. Multi-Level 3-to-8 Decoder Level 1 3-to-8 Line decoder Level 2 2-to-4 Line decoder using Level 3: 1-to-2 Line decoder Build 3-to-8 Line decoder using level 2 & level 1 decoders with 8 2-input AND gates

  10. Enable Used for Expansion

  11. …. = C0B0 B0, B1, B2, …, B7 D7= C0B7 … D8= C1B0 D15= C1B7 C0, C1, C2, …, C7 = C7B7 Multi-Level 6-to-64 Decoder …. ...

  12. Uses for Decoders • Binary number might serve to select some operation • Computer operation codes are encoded • Decoder lines might select add operation, or subtract operation, or multiply operation, etc. • Memory address lines

  13. Variations • At right • Enable not • Inverted outputs

  14. Combinational Logic Implementation ExampleUsing a Decoder and OR Gates + + + + + + • Implement the following 3 odd parity functions of the 4 variables (A7, A6, A5, A4)P1 = A7 A5 A4P2 = A7 A6 A4P4 = A7 A6 A5

  15. Combinational Logic Implementation Example Using a Decoder and OR Gates + + + + + + • Implement the following set of odd parity functions of (A7, A6, A5, A4)P1 = A7 A5 A4P2 = A7 A6 A4P4 = A7 A6 A5 • Finding sum ofminterms expressions P1 = Sm(1,2,5,6,8,11,12,15)P2 = Sm(1,3,4,6,8,10,13,15)P4 = Sm(2,3,4,5,8,9,14,15)

  16. Decoder and OR Gates Example P1 A7 A6 A5 A4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + + + + + + P2 P4 • Implement the following set of odd parity functions of (A7, A6, A5, A4)P1 = A7 A5 A4P2 = A7 A6 A4P4 = A7 A6 A5 • Finding sum ofminterms expressions P1 = Sm(1,2,5,6,8,11,12,15)P2 = Sm(1,3,4,6,8,10,13,15)P4 = Sm(2,3,4,5,8,9,14,15) • Find circuit

  17. In General: Combinational Logic Implementation Using a Decoder and OR Gates • Implement m functions of n variables with: • Sum-of-minterms expressions • 1 decoder; n-to-2n-line (e.g. 4-to-16-line decoder) • mOR gates, one for each function (e.g. m = 3) • Solution • Find the minterms for each output function • OR the minterms together

  18. Encoder • Encoder is the opposite of decoder • 2n inputs • or less – 10 inputs in “Decimal to BCD” encoder: I0, I1, I2, I3, …, I9 • n outputs • 4 output lines “Decimal to BCD”encoder

  19. Truth Table: 8-to-3 Binary Encoder

  20. Inputs are Minterms • Can OR the minterms appropriately to get each of the outputs A0, A1, A2 • Example: A0 = D1 + D3 + D5 + D7

  21. Generating Outputs using OR of Minterms • A0 = D1 + D3 + D5 + D7 • A1 = D2 + D3 + D6 + D7 • A2 = D4 + D5 + D6 + D7

  22. What’s the Problem? = 1 • What if D3 and D6 both high? • A0 = D1 + D3 + D5 + D7 • A1 = D2 + D3 + D6 + D7 • A2 = D4 + D5 + D6 + D7 • Simple OR circuits will set A (the output) to 7 = 1 = 1

  23. Priority Encoder • if more than one input is true, produce the code of the input with highest priority • i.e. Largest number, usually • Note “don’t cares” What if all inputs are zero?

  24. Need Another Output • A “Valid” output

  25. Hide Hide Figure 3-24 Figure 4-12 Logic Diagram of a 4-Input Priority Encoder Valid is OR of inputs Hide

  26. K Map for A0 • X on an input means the circuit must generate the specified output value for both input possibilities: 0, 1 • A0 = D3 + D1 D2’ • A1 = D2+ D3

  27. A0 = D3 + D1 D2’ A1 = D2 + D3 V = D0 + D1 + D2 + D3 Figure 3-24 Figure 4-12 Logic Diagram of a 4-Input Priority Encoder Circuit of Priority Encoder

  28. Data Selector (2 to 1 Multiplexer) I0 Y I1 s Multiplexers Example: Two Input Multiplexer • If s = 0, Y = I0 , else Y = I1

  29. Two Input Mux

  30. Two Input Mux

  31. Multiplexers: • A multiplexer selectsinformation from aninput line and directs the information to anoutput line • A typical multiplexer has • nselection control inputs (Sn - 1, … S0) • 2n information data inputs (I2n- 1, … I0) • one output Y

  32. Multiplexers (continued) • A multiplexer can be designed to have • n selection inputs • m information inputs with m < 2n

  33. I0 I1 I2 I3 I0 I1 I2 I3 4-to-1-Line Multiplexer A Single Bit 4-to-1 Line Multiplexer

  34. A Single Bit 4-to-1 Line Multiplexer(cont.) Logic is a Decoder Plus4 X 2-Input AND gates feeding an OR gate

  35. Quad 2-to-1 Mux • Select 1 of 2 sets of lines: A & B; • Practical use: Select a whole 64-bit data bus from one of two sources each set has 4 lines

  36. Gate input count is 18 Three-State Implementation:A Single Bit 4-to-1 Line Multiplexer

  37. Binary Tree StyleThree-State Implementation:A Single Bit 4-to-1 Line Multiplexer Gate input count is 14

  38. Multiplexer-Based Combinational Circuits- Approach 1 • Implement m functions of n variables with: • Sum-of-minterms expressions • Use an m-wide 2n-to-1-line multiplexer

  39. Example: Gray to Binary Code Converter Gray Binary A B C x y z 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 1 0 1 1 0 1 1 1 0 0 0 1 1 1 1 • Design a circuit to convert a 3-bit Gray code to a binary code • Implement m=3 functions (x,y,z) of n=3 variables (A,B,C) with: • Sum-of-minterms expressions • Use an m-wide (3-wide) 2n-to-1-line (8-to-1) multiplexer

  40. Example: Gray to Binary Code Converter Gray Binary A B C x y z 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 1 0 1 1 0 1 1 1 0 0 0 1 1 1 1 • It is obvious from thistable that X = C, howeverY and Z are more complex

  41. Gray to Binary (continued) • Rearrange the table sothat the input combinationsare in counting order • x = C; functions y and z can be implemented usinga dual 8-to-1-line multiplexers as follows: • connect A, B, and C to the multiplexer select inputs: S2, S1, S0 • place y and z on the two multiplexer outputs • apply their respective truth table values to the inputs

  42. Gray to Binary (continued) 0 0 D10 D00 1 D11 D01 1 1 D12 D02 1 0 D13 D03 0 D14 1 0 D04 Out Z Y Out 0 1 D15 D05 0 1 D16 D06 1 D17 0 D07 A S2 A S2 8-to-1 8-to-1 S1 B S1 B MUX MUX S0 S0 C C

  43. Implementation of any m functions of n variables using an m-wide 2n-to-1 multiplexer: Approach 1 • Find the truth table for the functions • In the order they appear in the truth table: • Apply the function input variables to the multiplexer selection control inputs Sn - 1, … , S0 • Label the outputs of the multiplexer with the output functions • Value-fix the information inputs of the multiplexer using the values from the truth table (for don’t cares, apply either 0 or 1)

  44. Combinational Logic Implementation- Multiplexer Approach 2 • Implement any m functions of n + 1 variables by using: • An m-wide 2n-to-1-line multiplexer • A single inverter

  45. Example: Gray to Binary Code Converter Gray Binary A B C x y z 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 1 0 1 1 0 1 1 1 0 0 0 1 1 1 1 • Implement any m functions of n + 1 variables using: • An m-wide 2n-to-1-line multiplexer • A single inverter • Implement any 3 functions of 2 + 1 variables using: • An 3-wide 22-to-1-line multiplexer • A single inverter

  46. Example: Gray to Binary Code Converter Gray Binary A B C x y z 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 1 0 1 1 0 1 1 1 0 0 0 1 1 1 1 • Implement the 3 functions: x, y, z of 2 (A, B) + 1 (C) variables by using: • An 3-wide 22-to-1-line multiplexer • A single inverter

  47. Gray to Binary (continued) F = C F = C F = C F = C F = C F = C F = C F = C • Rearrange the table so that the input combinations are in counting order • pair rows • find rudimentary functions

  48. Gray to Binary (continued) C C D10 D00 D11 C C C C C D01 C D12 Y Out Z D02 Out C C D13 D03 4-to-1 4-to-1 A A S1 S1 MUX MUX S0 S0 B B • Assign the variables & functions to the multiplexer inputs/outputs • Note that this approach (Approach 2) reduces the cost by almost half compared to Approach 1.

  49. Combinational Logic Implementation- Multiplexer Approach 2 C C • Implement any m functions of n + 1 variables by using: • An m-wide 2n-to-1-line multiplexer • A single inverter • Design: • Find the truth table for the functions. • Based on the values of the first n variables, separate the truth table rows into pairs • If the n+1 variable is C, then the set of rudimentary functions defined on C is S = (0, 1, C, ) • For each pair of rows of the truth table and output, choose the correct rudimentary function, F(C) of the variable C from the set S • Using the first n variables as the index, value-fix the information inputs to the multiplexer with the corresponding rudimentary functions • Use the inverter to generate the rudimentary function

  50. 1-to-4-Line Demultiplexer Demultiplexer • Takes one input • Out to one of 2n possible outputs

More Related