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EECS150 - Digital Design Lecture 12 - Combinational Logic Circuits Part 3

EECS150 - Digital Design Lecture 12 - Combinational Logic Circuits Part 3. March 4, 2002 John Wawrzynek. In the News. Multiplication. a 3 a 2 a 1 a 0 Multiplicand b 3 b 2 b 1 b 0 Multiplier X a 3 b 0 a 2 b 0 a 1 b 0 a 0 b 0 a 3 b 1 a 2 b 1 a 1 b 1 a 0 b 1 Partial

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EECS150 - Digital Design Lecture 12 - Combinational Logic Circuits Part 3

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  1. EECS150 - Digital DesignLecture 12 - Combinational Logic Circuits Part 3 March 4, 2002 John Wawrzynek EECS150 - Lec12-cl3

  2. In the News ... EECS150 - Lec12-cl3

  3. Multiplication a3 a2 a1 a0Multiplicand b3 b2 b1 b0Multiplier Xa3b0 a2b0 a1b0 a0b0 a3b1 a2b1 a1b1 a0b1 Partial a3b2 a2b2 a1b2 a0b2 products a3b3 a2b3 a1b3 a0b3 . . . a1b0+a0b1 a0b0Product Many different circuits exist for multiplication. Each one has a different balance between speed (performance) and amount of logic (cost). EECS150 - Lec12-cl3

  4. Sums each partial product, one at a time. In binary, each partial product is shifted versions of A or 0. Control Algorithm: 1. P  0, A  multiplicand, B  multiplier 2. If LSB of B==1 then add A to P else add 0 3. Shift [P][B] right 1 4. Repeat steps 2 and 3 n-1 times. 5. [P][B] has product. “Shift and Add” Multiplier • Cost  n,  = n clock cycles. • What is the critical path for determining the min clock period? EECS150 - Lec12-cl3

  5. “Shift and Add” Multiplier Signed Multiplication: Remember for 2’s complement numbers MSB has negative weight: ex: -6 = 110102 = 0•20 + 1•21 + 0•22 + 1•23 - 1•24 = 0 + 2 + 0 + 8 - 16 = -6 • Therefore for multiplication: a) subtract final partial product b) sign-extend partial products • Modifications to shift & add circuit: a) adder/subtractor b) sign-extender on P shifter register EECS150 - Lec12-cl3

  6. Array Multiplier Generates all partial products simultaneously. Each row: n-bit adder with AND gates. What is the critical path? Delay  ?, cost  ? EECS150 - Lec12-cl3

  7. Speeding up multiplication is a matter of speeding up the summing of the partial products. “Carry-save” addition can help. Carry-save addition passes (saves) the carries to the output, rather than propagating them. Example: sum three numbers, 310 = 0011, 210 = 0010, 310 = 0011 310 0011 + 210 0010 c 0100 = 410 s 0001 = 110 310 0011 c 0010 = 210 s 0110 = 610 1000 = 810 Carry-save Addition carry-save add carry-save add carry-propagate add • In general, carry-save addition takes in 3 numbers and produces 2. • Whereas, carry-propagate takes 2 and produces 1. • With this technique, we can avoid carry propagation until final addition EECS150 - Lec12-cl3

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  9. Array Multiplier with Carry-Save EECS150 - Lec12-cl3

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  12. CL Circuits from Mano • Magnitude Comparator • Multiplexors (revisited) • Decoders • basic • hierarchical • Encoders • standard • Priority Encoder EECS150 - Lec12-cl3

  13. We studied magnitude comparators in CS61c as part of the MIPS processor design. What was that method? Why that then and not now? Magnitude Comparator (A>B) = A3B’3 + x3A2B’2 + x3x2A1B’1 + x3x2x1A0B’0 (A>B) = A’3B3 + x3A’2B2 + x3x2A’1B1 + x3x2x1A’0B0 (A=B) = x3x2x1x0 EECS150 - Lec12-cl3

  14. Multiplexors Revisited • Basic AND/OR form • NAND/NAND • tristate buffer based • transmission gate based • hierarchical • decoder based • delay analysis EECS150 - Lec12-cl3

  15. Decoders EECS150 - Lec12-cl3

  16. Hierarchical Decoders EECS150 - Lec12-cl3

  17. Generates binary code at output corresponding to input code. Example: one-hot to binary encoder. (Opposite of decoder) a b c d x y 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 0 0 0 1 1 1 Priority Encoder: If two or more inputs are equal to 1 at the same time the input with the highest “priority” will take precedence. Example: a b c d x y V 0 0 0 0 - - 0 1 0 0 0 0 0 0 - 1 0 0 0 1 1 - - 1 0 1 0 1 - - - 1 1 1 1 “V” is the valid signal, “d” has highest priority. Encoders EECS150 - Lec12-cl3

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