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The MROD

The MROD. The MDT Precision Chambers ROD Adriaan K önig University of Nijmegen. Contents. • System Overview • MROD-0 Prototype • MROD-1 Prototype • Performance Study • FE Parameter Loading & Initialization • Names. TDC 1. TDC 1. CSM. CSM. 18 x. 18 x. TDC 18. TDC 18.

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The MROD

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  1. The MROD The MDT Precision Chambers ROD Adriaan König University of Nijmegen ATLAS MDT Electronics PDR

  2. Contents • System Overview • MROD-0 Prototype • MROD-1 Prototype • Performance Study • FE Parameter Loading & Initialization • Names ATLAS MDT Electronics PDR

  3. TDC 1 TDC 1 CSM CSM 18 x 18 x TDC 18 TDC 18 System Overview Chamber Tower MROD CSM-Link 6 x 1.28 Gbit/s S-Link to ROB CSM-Link ATLAS MDT Electronics PDR

  4. 1 S 18 CSM-MUX Functionality 40 Mbit/s Data/Strobe from TDC CSM-MUX Serial to Parallel & Clock Domain Separator 1 Gbit/s Separator 18 x 40 Mbit/s Data/Strobe from TDC (CSM-Link) Serial to Parallel & Clock Domain Separator 1 Start bit 32 Data bits 1 Parity bit 1 Stop bit 35 bits @ 25 ns = 875 ns 1 Separator word (S) 18 TDC data words 19 words in 875 ns  87 MB/s ATLAS MDT Electronics PDR

  5. MROD Function Separator word Check (do not store) TDC0, word 1 Build events in a partitioned memory from TDC data fragments (tdc 1) 000…000 Skip (do not store) time TDC2, word 4 TDC3, word 2 Separator word TDC0, word 1 TDC1, word 3 TDC2, word 5 TDC3, word 3 TDC2, word 3 Separator word TDC1, word 2 TDC2, word 2 (tdc 0) 000…000 TDC1, word 1 TDC2, word 1 TDC3, word 1 TDC0, word 0 TDC1, word 0 TDC2, word 0 TDC3, word 0 ATLAS MDT Electronics PDR

  6. CSM-Link CSM-Link CSM-Link CSM-Link CSM-Link CSM-Link MROD Throughput MROD MROD input MROD input MROD output MROD input S-Link MROD input 1.28 Gbit/s (» 128 MB/s) MROD input MROD input Average 5 hits per TDC + header + trailer = 7 words/event Per tower of 6 chambers max. 88 TDCs * 7  600 words/event (= 2.4 kB/event) Worst case est.: @ 100 kHz L1A rate  240 MB/s per MROD Calculation based on actual tower layout (J.Chapman): max. rate < 60 MB/s per MROD ATLAS MDT Electronics PDR

  7. MROD Form Factor • • 9 U VME board (single slot), 6 Input Links, 1 S-Link Output • • Optionally 2 extra Input Links with “extension” board to • accommodate special towers with > 6 chambers • Input and Output Link Interfaces on main board • • SHARC II (ADSP21160), 2.5 x faster than 21060 • • 1 MROD Crate contains: • 12 MRODs (12  Segments) • Max. 4 MROD Extension Boards • 1 Standard (?) Crate Master with Ethernet Interface (DetDAQ) • 1 TTC-Rx Interface Module • 1 Busy Module ?? • 1 DCS Interface Module ?? • • @ 192 towers: 192/12 = 16 MROD Crates (1 per  Sector) ATLAS MDT Electronics PDR

  8. MROD Crate DAQ / DCS Network ROB ROB VME-bus “TTC-bus” LDAQ MROD … total ... 12 x MROD TTCrxInterface Module ROD Busy Module 6 CSMs 6 CSMs From TTC system One MROD Crate services 12 towers (e.g. one full sector). In total 16 crates will be required for all MDT chambers. Some MRODs may have 7 or 8 input links via “slave” MROD input cards. ATLAS MDT Electronics PDR

  9. MROD-0 Prototype sorted TDC-data over SHARC Link MRODIN MRODOUT MCRUSH SHASLINK PCISHARC ATLAS MDT Electronics PDR

  10. MROD-0 Input Channel MCRUSH 1 MB ZBT Memory Input FIFO Output Tetris Register FIFO Control SHARC 6 Sharc links @ 40 MB/s each Data FIFO Length FIFO FPGA Control/Status Error signaling ATLAS MDT Electronics PDR

  11. MROD-0 Output Channel SHaSLINK PCI bus SHARC PCI 9054 6 SHARC Links @ 40 MB/s each Altera 10K10A S-Link max. @ 160 MB/s ATLAS MDT Electronics PDR

  12. (SHARC) ATLAS MDT Electronics PDR

  13. Memory FPGA MROD-1Prototype SHARC VME64x FPGA Memory SHARC (2x) SharcLinks 3x (intotal) Memory FPGA TTC Interface SHARC FPGA Memory ATLAS MDT Electronics PDR

  14. SHARC-II ATLAS MDT Electronics PDR

  15. The ADSP-21060 and the ADSP-21160 SHARCs • • 40 MHz / 80  100 MHz CPU (SIMD mode) • 512 KB/512 KBinternal memory • 6 x40/ 80  100MB/s links. Throughput of all links simultaneously • is 160 / 480  600 (?) MB/s, without disturbing the CPU. • No handshaking on links, but hardware XON-XOFF protocol, • 10 / 14DMA channels • Support for bus arbitration: at max. 6 SHARCs can be connected to a common • bus without glue logic. Each SHARC can access the internal memories of each other • SHARC. The SHARCs also provide support for a so-called host interface, which can • act as an additional master on the common bus. • Fast interrupt servicing due to the presence of shadow registers • Two 40 Mbit/s / 40  50 Mbit/s (at max.) synchronous serial ports • Can be booted via link 4 ATLAS MDT Electronics PDR

  16. MROD-1 Form Factor S-Link daughter boards • •9 U VME board, 6 S-Links in, 1 S-Link out • S-Link interfaces on daughter boards • • SHARC II (ADSP21160), 2 x faster than 21060 • (3 for input, 2 for output processing) • Altera APEX FPGAs, 200k gates • TTC interface over special back plane • VME64x interface Input Input Input Output Motherboard ATLAS MDT Electronics PDR

  17. ATLAS MDT Electronics PDR

  18. MROD-1 Status & Planning • VHDL design of FPGAs finalized. • MROD-1 modules available by July 2001. • Tests/performance measurements at NIKHEF. • Read-out system of BOL test-stand (5 MDTs) at NIKHEF with special TDC32 CSM-MUX. • System integration tests with CSM, ROB and DAQ test set-up (possibly in test-beam). ATLAS MDT Electronics PDR

  19. MROD Performance Study MROD CSM MRODIN CSM MRODIN MRODOUT CSM MRODIN ROB CSM MRODIN CSM MRODIN MRODIN CSM ATLAS MDT Electronics PDR

  20. CSMSIM SHASLINK 0 MROD Emulation Hardware Region-of-Interest Requests, Decision Records, etc., everything needed to run a ROBIN simulation MROD-0 sorted + merged TDC-data sorted TDC-data TDC-data MRODIN (3x) MCRUSH MRODOUT SHASLINK ROBIN CRUSH RoIRR ROBSIM SHASLINK 2 2 2 0 RoID/ T2OD 0 0 3 1 0 1 3 4 4 fragment lengths sorted TDC-data 4 RoIR/ T2DR 4 PCISHARC xxxxx Module type S-Link optionally double/triple MRODIN output thus simulating 2 or 3 MRODINs SHARC-link event fragment lengths via SHARC-link simulates future MROD-1 functionality (PCI-)interface to host PC ATLAS MDT Electronics PDR

  21. MROD CSMSIM MRODIN MRODOUT ROBIN ROBSIM ATLAS MDT Electronics PDR

  22. MROD Performance Study Results MROD CSMSIM MRODIN MRODOUT ROBIN ROBSIM ATLAS MDT Electronics PDR

  23. MROD Performance Study Results MROD CSMSIM MRODIN MRODOUT ROBIN ROBSIM ATLAS MDT Electronics PDR

  24. MROD Performance Study Results MROD CSMSIM MRODIN MRODOUT ROBIN ROBSIM ATLAS MDT Electronics PDR

  25. MROD Performance Study Results MROD CSMSIM MRODIN MRODOUT ROBIN ROBSIM ATLAS MDT Electronics PDR

  26. MROD Performance Study Results MROD CSMSIM MRODIN MRODOUT ROBIN ROBSIM ATLAS MDT Electronics PDR

  27. MROD Performance Analysis • Measured event rate for single output SHARC @ 40 MHz with 3 input channels:event rate  min(50,1000/(10 + #words-per-CSM/6)kHz. • MROD-1 uses SHARC-II @ 80 MHz: both processing speed and bandwidth increase proportionately  event rate  100 kHz ? • ‘Final’ MROD: SHARC-II @ 100 MHz. ATLAS MDT Electronics PDR

  28. FE parameter loading/initialization TTC MDT-DAQ TDCs ASDs CSM MROD ROB CSM Link Mezzanine boards DCS JTAG routing: ATLAS MDT Electronics PDR

  29. JTAG Usage • Initialize/Set/Reset ASD/TDC/CSM parameters • Reload CSM parameters and flash memory (if/when needed) • Timing calibration sequence: 1: JTAG enables calibration pulses in the ASD 2: TTC signals the CSM to send a test pulse 3: TTC subsequently provides a calibration trigger  No calibration during regular data taking since JTAG clock (TCK) must remain turned off to avoid noise in the ASDs. ATLAS MDT Electronics PDR

  30. MROD Names (NIKHEF and Univ.of Nijmegen) • Henk Boterenbrood • Peter Jansweijer • Gerard Kieft • Adriaan König • Jos Vermeulen • Thei Wijnen • NN (Post-doc vacancy at Univ.of Nijmegen: www.hef.kun.nl/vac-postdoc.html) ATLAS MDT Electronics PDR

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