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Preparatory Design Studies MROD-X. Use Xilinx Virtex II Pro Rocket IO Power PC Port the current MROD-In design from Altera to Xilinx. Altera APEX20K200EQC240-1 Total logic elements 5605 / 8320 (67 %) Total ESB bits 15360 / 106496 (14 %) Total pins 168 / 171 (98 %). Xilinx
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Preparatory Design StudiesMROD-X • Use Xilinx Virtex II Pro • Rocket IO • Power PC • Port the current MROD-In design from Altera to Xilinx
Altera APEX20K200EQC240-1 Total logic elements 5605 / 8320 (67 %) Total ESB bits 15360 / 106496 (14 %) Total pins 168 / 171 (98 %) Xilinx XC2VP7FG456-7 Number of SLICEs 2898 out of 4928 (58%) Number of RAMB16s 3 out of 44 (6%) Number of External IOBs 168 out of 248 (67%) MROD-In design fromAltera to Xilinx Note 1: Rule of thumb 70 % = FULL. If you try to put more in your FPGA then you’ll probably face routing and timing problems! Note 2: 1 Xilinx “SLICE” (~ 2 “Logic Cells”) ~ 2 Altera “Logic Elements”
GOL to RocketIO test GOL Test Board Development Board Xilinx Virtex-II Pro FPGA Start Insert Error Reset Status LEDs 50 MHz 25 MHz Event Data ROM Altera FPGA Idle 1 Gb/s Run Event Data ROM Rocket IO GOL = ? Okay Fault
GOL to RocketIO testResults • Xilinx ISE RocketIO placement problem -> Solved • Back-annotated simulation of the setup -> Okay! Reset Start Insert Error + Start • Real life test -> Okay!
To Be Done:Test FPGA to FPGA Data Links Plus Flow Control Development Board Evaluation Kit Xilinx Virtex-II Pro FPGA Xilinx Virtex-II Pro FPGA 1.6 Gb/s (160 MB/s) Full Empty FIFO Rocket IO Rocket IO FIFO Data Data
Power PC core Evaluation • Learn to use Xilinx Embedded Development Kit (EDK) • Play with the demos that were delivered with the boards • Made LED On/Off via RS232 system, using PPC core + Peripherals.
PPC-Core PLB Arbitter PLB BRAM Controller BRAM PLB 2 OPB Bridge OPB Arbitter Processor Reset UART-Lite JTAG PPC controller Xilinx XC2VP7FF869-6 PPC405s 1 out of 1 100% RAMB16s (2 KByte each) 16 out of 44 36% Number of SLICEs 826 out of 4928 16% Power PC Hello World System
Conclusions: • Design can easily be ported from Altera to Xilinx • RocketIO • GOL Receiver is working. • Inter FPGA link to be tested. • Power PC • Consumes FPGA resources (probably need a XC2VP20 instead of a XC2VP7 device) • Needs investment in learning EDK • Needs investment in software development
MROD-In design fromAltera to Xilinx Altera APEX20K200EQC240-1 • Total logic elements • 5605 / 8320 (67 %) • Total ESB bits • 15360 / 106496 (14 %) • Total pins • 168 / 171 (98 %) • Worst Case timing • IO pin to ZBT memory data line: 805 ps left… Xilinx XC2VP7FG456-7 • Number of SLICEs • 2898 out of 4928 (58%) • Number of RAMB16s • 3 out of 44 (6%) • Number of External IOBs • 168 out of 248 (67%) • Worst Case timing • Clkx2 -> WrSharc_n: 40 ps left. Note 1: Rule of thumb 70 % = FULL. If you try to put more in your FPGA then you’ll probably face routing and timing problems! Note 2: 1 Xilinx “SLICE” (~ 2 “Logic Cells”) ~ 2 Altera “Logic Elements”
First Rough Worst Case Timing Estimate • XC2VP7FG456-5 Fail 2 Constraint (-35 ps) • XC2VP7FG456-6 Fail 1 Constraint (-11 ps) • XC2VP7FG456-7 Okay (40 ps) • XC2VP7FF896-5 Fail 1 Constraint (-884 ps) • XC2VP7FF896-6 Okay (23 ps) • XC2VP7FF896-7 Okay (25 ps) Xilinx fitter tries to exploit the full timing budget that is set in the constaints file. Therefore conclusions are hard to make… Failed constraints are on “Clkx2” (80 MHz)
