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Some remarks to the FADC+proc, what exists and... and SVD-2 read out system

Some remarks to the FADC+proc, what exists and... and SVD-2 read out system. The 3 steps of FIFO’s for normal 6 time one hit information read out time calculation for 16 inputs 20 % occupancy on every time slice. Pipe line. 154 3,85 µs. ready, tested with VME read out

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Some remarks to the FADC+proc, what exists and... and SVD-2 read out system

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  1. Some remarks to the FADC+proc, what exists and... and SVD-2 read out system M. Pernicka

  2. The 3 steps of FIFO’s for normal 6 time one hit information read out time calculation for 16 inputs 20 % occupancy on every time slice Pipe line 154 3,85 µs ready, tested with VME read out final memory waiting for ext control signal and Finesse data read out Proc FIFO-1 2K Altera_N 32 bit data position + header+.. 40 MHz Proc 154 3,85 µs Proc Only 0ne FIFO-2 16K*72 614 data 15,36 µs Proc 154 3,85 µs Pipe line FIFO-1 2K Proc <31µs Final data block Main memory spy memory To finesse Proc <62µs 154 3,85 µs < 31µs Proc 40 MHz 32 + 4 bit Altera_Nc M. Pernicka Proc

  3. In Future: Could be 2 trigger in a time distanc smaler than 3,85 µs? How many trigger could be in a certain time? How fast is the cooper system? How many interaption we have to expect. There could be a noise problem and we would get a lot to much data and the 3 steps of FIFO's are nearly full than busy and the amount of data which are stored in FIFO-1 for an event will be M. Pernicka

  4. The 3 steps of FIFO’s for hit with time information read out Data with Hit information All data are stored +hitinf 8 bit +1 768 data 19.2 µs 768 data 840*25ns= 21 µs FIFO-1 2K Altera_N Planed for future Only 0ne FIFO-2 16K*72 Pipe line 768 data 840*25ns= 21 µs FIFO-1 2K Reorder data Strip data with one max or not Time calculation on board or outside To VME <40µs fixed time To Finesse <40µs Altera_Nc Sec. half M. Pernicka

  5. Fast Signals for the data transfer between FADC + processor and Finesse Da ta finesse Nearly full: FADC has to stop data transfer after 4-5 more data and / or do not send data, wait FADC + processor 32 bit data, daen, header, trailer + HA_EV synchronic to clock an Clock: has to optimal adjusted to the data, done on FADC Control Finesse Busy Minimum one of the FADC is on the limit of his data memories ( can also result in reduced event data block?) M. Pernicka

  6. For test purpose Single FADC+proc connected to control- and data Finesse Exist but untested 96 Pin Data 32 Data bus XD_0=bis XD_31 4 control lines DA_EN, HALF_EV, TRAILER.HEADER DCLK clock 40 MHz BSYFD busy Finesse 2 spare will be used for WR and RE, reserve for later ?, P - 3 DC/DC + 5 V/ -5 Volt P – 3 ADCRST;TRG; SCK, TAG0-7, TYP0, / TYP1-3 will be included in new version . 50 pin control ADCBSY (BUSSY), ADC_ERR (ERROR!_CON), for single use OK, SPARE1_WR_CON 2 spare will be used for WR and Re, reserve for later ? For the module busy ADCBSY (BUSY_COM ) ADC_ERR ; open Collector output M. Pernicka

  7. The use of bit 31 – 0 for the different data types decided by VME command * With or with out neighbours OR* OR OR* Hit + transp. Date, test Finesse Input header Transparent data Hit date Hit + time date Input Trailer Main trailer Main header 31=type of trailer =0 31=1 30,29 quality of data and type 31 type header = 1 30-27 trigger type/4 25-23 type of data / 3 31=type of trailer=1 31typ of header =0 31-23 transpar. Data after reorder need a window 31-23=0 transparent data belong to the hit 31-23 transp data ADC, some times or cont. date 0 Input 1 - 10, 11 - 21, 23 - 34 ----------- 49 - 58 60 - 69 71 - 82 29-23 event number from input. 28-23 Time of hit may be error bits ? Bit 15 - 0 = 1 22-20 time block 3 22-20 time block 3 * 20-16 time of clock/ trig inclu de later Alt-C 5 19-16 input = 4 19-16 input = 4 19-16 input = 4 ? 19-16 input = 4 19-16 input = 4 15-0 ? CRC ? code 15 crate ? 13-9 module n Alt-C 15-9 Ped Correction-2 7 15-9 position 7 15-9 position 7 15-9 position 7 ??? 8-0 Pulse height data 9 8-0 Pulse height if found 8-0 Pulse height data 9 8-0 Pulse height data 9 8-0 Ped Correction-1 9 7-0 Event number, from Copper syst. /8 May be the trggertime data gets more bit M. Pernicka * 22..20 = 0 than no hit data

  8. About up speed of the SVD-2 System Started! At the beginning some problem to understand our thinking some years ago. Today may be we would do it different. Most simple solution would be to double the write in frequency for the first FIFO , reduce the time window (half) and adjust new the start and stop bit. The module works with 40 MHz and we reduce only the final read out speed to the PCI link. Advantage faster data transfer on the module and slightly better used FIFO’s In this System the FIFO’s are not very big. The “BUSY” system could be improved to be able to store a little more data on the module The PCI link card could in include in future a “ FIFO “ It is foreseen to install a SVD-2 read out system without PCI link but VME read out and a simulation for the 2 PCI link signal XENABLE and XREADY. In a month we should have a crate to proof the speed up wish! M. Pernicka

  9. Timing of the data transfer of the SVD-2 system 4*128*16 bit FIFO one event VATA 1-4 128 data*100 ns (10 MHz) = 12,8 µs ( first step 4 event buffer) 12*128 data (16 bit)*50 ns (20 MHz) 76,8 µs 12 inputs 12*128 (32 bit) 76,8 µs (20MHz) 32*4096 FIFO < 2.66 events final memory 12inputs M. Pernicka 38.4 µs

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