Physical Design of FabScalar Generated Cores

1. Physical Design of FabScalar Generated Cores EE6052 Class Project Wei Zhang

2. Outline • FabScalar Toolset • Synthesis • Physical design using IC Compiler – Problems and solutions • Things to do next Wei

3. FabScalar Toolset • FabGen: This tool generates synthesizable RTL of a superscalar core based on user-specified parameters:* Frontend superscalar width* Backend superscalar width* Pipeline depths of canonical pipeline stages* Issue queue size. • FabMem: This tool estimates read/write delays, read/write energies, and area of user-specified multi-ported RAMs/CAMs. It can also generate layouts of desired RAMs/CAMs. Wei

4. Synthesis • FebGen-generated RTL is synthesizable. • Before starting synthesis • Comment-out the verification components to remove unsynthesizableverilog needed for simulation only: VPIs (the verilog/C++ co-simulation environment) and performance counters. • Memory handling • Use FabMem to generate custom designs of these critical memory structures, including full layouts, SPICE netlists, and LEFs. • During synthesis, remove the behavioral modules of the memory structures and constrain their input-port and output-port timing paths based on timing numbers from SPICE simulation. • For place-and-route, use the LEFs to represent the memory structures. Wei

5. Physical Design – Problems Encountered • ICC reports errors when importing netlist generated from synthesis. • Error message examples from ICC • Error: Can not create instance master 'SRAM_4R8W' in FRAM view. (MWDC-001) • Error: Can not create instance master 'CAM_4R4W' in FRAM view. (MWDC-001) • Warning message examples from synthesis • Warning: Unable to resolve reference 'SRAM_4R8W' in 'InstructionBuffer'. (LINK-5) • Warning: Unable to resolve reference 'CAM_4R4W' in 'IssueQueue'. (LINK-5) • Cause of the errors • No corresponding memory cells in the Milkyway library. • FabMem uses 45nm FreePDK library and our design uses the 90nm EDK library. Wei

6. Physical Design – Problem Solutions • Solution – Adapt the memory blocks generated from the FabMem tool to the 90nm technology. • The FabMem tool could generate layouts of memories, from which we can get the GDSII files. • To adapt these layouts to the 90nm technology, we need to modify the GDSII files to • Double the size of each physical component in the layout. • Map each layer in the FreePDK library to these layers in the 90nm technology library. • Import these memory blocks to the Milkyway Library using the Milkyway Environment tool and the new GDSII memory files. Wei

7. Physical Design – Library Preparation • Before using IC Compiler, logical and physical libraries must be created that accurately reflect the characteristics of the available technology and cells that will be used to fabricate the chip. • FabScalar generated cores use a lot of RAM/CAM blocks, most of which are multi-ported. • The standard cells are already provided in the 90nm physical library, but macros like memory blocks are not provided. • The memory blocks must be created in the physical library. This can be done in the Milkyway Environment. • Layout data of these memory blocks are provided by FabMem. (GDS and LEF) Wei

8. Physical Library Preparation – Memory Wei

9. Library Preparation Flow in the Milkyway Environment Wei

10. CEL View – SRAM_4R4W Wei

11. FRAM View – SRAM_4R4W Wei

12. Errors Before Adding Memory Physical Library Wei

13. Errors After Adding Memory Physical Library Wei

14. New Problems • Still missing a lot of instances in the physical library • 1ICache • PreDecode_PISA_3 • Decode_PISA_3 • SRAM_4R8W • SRAM_4R1W • Select_3 • ForwardCheck_7 • The “SRAM_4R8W”and “SRAM_4R1W”could not be generated from FabMem (only able to generate memories with XRXW and 2XRXW ports) • Most of the other instances are very similar to memories, but they are not standard memory blocks and could not be generated from FabMem. Wei

15. Problems Remaining • Still could not generate the remaining instances. • Could not move forward without these instances in the physical library. Wei