ITRS 2004-FEP Updates and Plans By J. Butterbaugh & C. Osburn, US FEP TWG Co-chairs

1. ITRS 2004-FEP Updates and PlansBy J. Butterbaugh & C. Osburn, US FEP TWG Co-chairs San Francisco, CA July 12-14, 2004

2. Starting Materials/Plans & Updates H. Huff and M. Walden co-chairs

3. Starting Materials, 2004 Updates • 2004 Table Updates: • Added long term years & requirements • Set introduction date of 450mm wafer to 2011 (colored red) • Made editorial corrections to table footnotes • Made changes to table color coding protocol

4. Potential Solutions: 2004 UpdateChange SOI to clear colorization in 2004 and cross-hatched shading in 2006 to ensure consistency with commercial reality

5. Starting Materials 2005 Plans • Review killer defect particle size (=1/2 technology node dimension) • Conduct new IDM surveys to establish 2005 requirement: • Wafer Orientation(s) and tolerances • Strained Silicon • 200 & 300mm backside particles, texture, and edge roll-off • SOI active layer thickness and tolerance for Fully Depleted Devices • Review wafer edge profile and edge roll-off for immersion lithography • Review site flatness requirements for consistency with Lithography requirements • Expand requirements tables for SOI and other emerging materials.

6. Surface Preparation J. Barnett and K. Reinhardt co-chairs

7. Surface Preparation2004 Update - Was / Is Analysis Tables 70a and 70b • Fill in Table 70b for added years: 2011, 2014, 2017 • Back Surface Particles – Plan to add metrics: Survey in Progress Footnotes for Tables 70a and 70b • Note [D] - rewrite when Back Surface metrics are established from survey • Note [E] - rewrite when Back Surface metrics are established from survey • Note [F] - Clarify classification of “Critical GOI” and “Critical Other” metals • Note [I] - Clarify basis for Surface Oxygen metrics • Note [J] - Plan to reference TI publication (pending) on the effects of surface roughness

8. Tables 70a/70b Footnote [I] Surface Preparation Technology Requirements—Long-term Front Surface Particles

9. Interconnect Surface Preparation2004 Update - Was / Is Analysis Tables 83a and 83b • Fill in Table 83b for added years: 2011, 2014, 2017 • Back Surface and Edge Particles – Plan to add metrics: Survey in Progress • Maximum Dielectric Constant Shift – Combine Rework, Strip, and Clean Footnotes for Tables 83a and 83b • Note [D] - rewrite when Back Surface metrics are established from survey • Note [E] - rewrite when Back Surface metrics are established from survey • Note [F] - rewrite when Edge metrics are established from survey Tables 64 • Wet cleaning chemistry potential solutions extending until hp32/1013 • Addition of pore sealing details – potential methodologies and timelines

10. Table 83a and b Interconnect Surface Preparation Technology Requirements —Near-term Requirements (shown) Dielectric Constant Delta: Take into Account Total Clean Process

11. Plans for 2005 • Front Surface Particles / Roughness / Material Loss • Work with YE to corroborate yield models • Develop model and add metrics for removal efficiency • Back Surface Particles • Develop model for back surface particles to support empirical metrics • Carbon/Oxygen • Establish requirements for high-k gate dielectrics • Metals/Mobile Ions • Establish requirements for high-k gate dielectrics • Interconnect Surface Preparation • Continue to work with Interconnect TWG • Establish requirement/potential solutions for pore sealing • YE-WECC Cross-TWG Interaction • Continue to work with YE-WECC to set metrics for UPW/Chemical/Gas purity

12. Critical Dimension Etch G. Smith and Y. Kim co-chairs

13. 2004 Updates • Introduce gate etch technical requirements for new long term years-2011,2014, 2017

14. Critical Dimension Etch-2005 Plans • 2004 Questionnaire validates the notion that 10% 3 control of the final etched gate length is not currently achieved. • Current “Red Walls” for both lithography and Etch • Problem worsens with further scaling of gate length • Variance contributions do not scale with gate length • 2004 Questionnaire also clarified current lithography and etch practices that are used to produce leading edge gate lengths • 2005 plans include: • Collaborate with Lithography TWG to re-allocate variance budgets to be more consistent with industry practice, and develop new etch requirements based on this allocations. • Collaborate with lithography, PIDS, and design TWG’s to identify ameliorating strategies and requirements.

15. THERMAL AND THIN FILM Updates/Plans C. Osburn and H. Huff co-chairs

16. 2004 Updates • Explanations Added in Footnotes - Allowable Gate Leakage Taken as 10/3 and 1/3 of Device Off- State - Leakage for High Performance and Low Power Application Respectively - Emphasis that Gate Leakage Spec is Valid for All Biasing Modes of Transistor - Recognition that Switch to High k and Metal Gates is Likely to Occur Together, Rather than Staggered • Editorial Corrections of Errors in 2003 Roadmap - Consistency in SiON Leakage (1/30 vs. 1/100 of Oxide) - Specification of Temperature Corresponding to Leakage Spec - Removal of Reference to DRAM Transistor Leakage • Requirements Values Generated and Added for 2011, 2014, and 2017

17. 2005 Roadmap AgendaGate Leakage • Re-Examine Gate Leakage Specifications • - Provide Rationale for Relationship of Gate Leakage Spec to Device • Off-State Leakage (if any) • - Consider Inverter Applications Which have Different Biasing • Configurations and Involve Both NMOS and (Different Sized) PMOS • - Involve PIDS and Circuit Design Communities • Include Specifications on PMOS Leakage (with PIDS) • - Including Observation that Area of PMOS Transistor is Larger • - Requires Parallel Activity of PIDS

18. 2005 Roadmap AgendaNon-Classical CMOS • Include Non-Classical CMOS Device Configurations • - Single Gate FD SOI • - FINFET • - Tri- and Multi-Gate Devices • Include Reqjuirements on Strained Layer Channels • - Mobility Enhancement Required (PIDS) • - Strain in Channel?, Thickness of Strained Layer? • (with Starting Materials) • - Non-Uniform Strain Requirements? (from Gate, STI) • - Stress in Layers? (with Starting Materials) • - Maximum Processing Temperatures? (with Doping)

19. 2005 Roadmap Agenda Shallow Trench Isolation • Expand on Shallow Trench Requirements (as feasible) • - Add Specification on n+ - p+ Spacing • - Provide Models to Quantify Tradeoffs Between Trench • Parameters, e.g., top rounding, bottom rounding, • angle, recess, etc.

20. Doping Updates/Plans H. Gossmann and M. Ieong co-chairs

21. 2004 Doping Updates • Generate Doping Requirements for years 2011, 2014, and 2017 • No other planned changes

22. 2005 Doping Initiatives • EOT, CET, and Poly-depletion • Source/Drain Extension Parameters: • Lateral abruptness • Junction Depth • Sheet Resistance • Contact Resistance • Bulk CMOS Devices • Non-classical CMOS Devices • Achieve internal consistency of PIDS assumptions and Doping Processes • Overall: Achieve Tighter coupling with PIDS

23. 2005 Initiatives • EOT, CET and Poly Depletion • Achieve EOT requirements for gate dielectric that are consistent with PIDS requirements for CET, and are consistent with model based values for polysilicon depletion, channel quantum effects, and metal gates • Extension Lateral Abruptness • For bulk devices improve on existing simplistic scaling law (0.11Lg) • Generate requirements for non-classical CMOS devices • Extension Junction Depth • Review current scaling rule (0.55Lg) to take into account the effect of halo implants • Is dopant activation with negligible diffusion really required? Are alternate strategies (halo + offset spacer) viable? • Review Xj requirements for non-classical ultra thin body devices • Extension Sheet Resistance • Review impact on requirements by use of metal gate & strained silicon channels • Possibly develop listing of dopant doses and implant energies required for a given resistance and depth profile • Determine whether current PIDS allocation between parasitic resistance and capacitance is still appropriate, and impact on offset spacer requirements

24. 2005 Doping Initiatives • Contact Resistance • Obtain better estimates for Bulk contact resistance requirements and required dopant concentrations • Review/upgrade requirements for non-classical CMOS devices • Tighter coupling with PIDS • PIDS will extend bulk parameters by an additional two nodes to provide overlap with two nodes having non-classical devices • Assure that this does not result in unphysical demands on doping processes • Close the loop with PIDS

25. Memory Updates/Plans DRAM Stack Capacitor- S. Sawada, M. Oda DRAM Trench Capacitor- M. Gutsche Flash Memory- M. Alessandri FeRAM-M. Kubota

26. Memory-2004 Updates • DRAM • Added requirements for years 2011, 2014 & 2017 • No other planned changes • FeRAM • 2005 feature size changed from 0.13 to 0.15  • Add requirements for years 2011, 2014, 2017 • Flash • Add Requirements for years 2011, 2014, 2017 • No other Changes Planned • Address differences in FEP and PIDS tables

27. Memory-2005 Plans • DRAM- revisit cell “a” factor forecast for Stack and Trench capacitors, and update requirements • FeRAM- Review and update requirements to reflect technology changes • Flash- A new Technology Driver? • A leading memory manufacturer has stated that Flash has become the technology driver • Will this become widespread? • Review the Flash requirements from this perspective, and ascertain impact on overall FEP difficult challenges. • Add requirements for new memory devices • MRAM, SONOS, PCM, Floating Body, …