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Panelists

Krste Asanovic [UC Berkeley]

euclid
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Panelists

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  1. Krste Asanovic [UC Berkeley] Krste received a BA in Electrical and Information Sciences from Cambridge University in 1987 and a Ph.D. in Computer Science from UC Berkeley in 1998. He then joined the faculty at MIT but couldn't cope with the Boston weather and managed to escape back to join the UC Berkeley faculty in 2007. He is currently working on many aspects of parallel software and hardware as part of UC Par Lab. Chita Das [NSF/Penn State] Chita is a professor in the Department of Computer Science and Engineering. His primary research interests include parallel and distributed computing, interconnection networks, performance evaluation and fault-tolerant computing. He is currently a program director at NSF managing the computer architecture program. Panelists

  2. Ran Ginosar [Technion] Ran Ran Ginosar got his BSc at the Technion in Israel and his PhD from Princeton University. He is a professor at the Technion, and has also visited with Bell Labs, University of Utah, and Intel Research. He co-founded several start-ups. His hobbies include VLSI architecture, asynchronous design and networks on chip. He is a co-founder of this conference and is heading its Steering Committee. Mike Kishinevsky [Intel] Mike leads a research group in front-end design at Strategic CAD Labs of Intel. He received his PhD degree from the Electro-technical University of St.Petersburg. Prior to joining Intel in 1998 Mike has been a Research Fellow at Russian Academy of Science,  a Senior Researcher at a start-up in asynchronous design, a visiting Associate Professor at the Technical University of Denmark, and a  Professor at the University of Aizu, Japan. Panelists (cont’d)

  3. Domain: NoCs in MPSoC vs. NoCs in CMPs - Are they really different? Related to this, how and what can the computer architects learn and contribute to/from the embedded/VLSI/DA communities. And vice versa? Workloads: Solution in search of a problem (supply chasing demand) - Are we are really seeing workloads demanding as much bandwidth as is being enabled in NoCs (e.g., photonics, RF)? Aren't we maybe over-hype the importance of NoCs? Programming model: NoC universal replacement? What type of systems/applications will benefit from NoCs? Which systems won’t? Questions

  4. Next big thing: What are the most urgent research issues we should address? Application specific or general purpose optimization? Verification or validation/testing? Maybe benchmarking and standardization of NoCs? Scope and impact (incl. education): What is the most compelling industrial benefit of NoC? What kind of results should sponsors (e.g., NSF, GRC, companies) expect over the next 5-10 years? How about the education of future engineers? Questions (cont’d)

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