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Non-layout Specific Questions

Non-layout Specific Questions. How important is stitching to module production? Can sensors be made of tiles that are diced into 10x10 cm 2 sections? Can sensors be built up of reticle -sized devices assembled elsewhere?

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Non-layout Specific Questions

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  1. Non-layout Specific Questions • How important is stitching to module production? • Can sensors be made of tiles that are diced into 10x10 cm2 sections? • Can sensors be built up of reticle-sized devices assembled elsewhere? • Would distributed dead regions in either case be an issue for tracking and, if so, how big can they be? • How does further reducing material affect tracking quantatively? • How should costs vs. material be balanced? • How can thinner collection volume to be used (less charge sharing)? Longer barrel region? No tilt angle to match Lorentz angle?

  2. Designs with Separate ASIC and ABCn-like FE • “Drop-in” • Easiest if all rectangluarand of same length • Do we need pointing strips in end cap? • How high can occupancy be? • I don’t think this is a problem; end cap over specified due to factor of 2 bug in occupancy (see backup if interested). 2.4 mm long strips in inner end cap radius would be 1.3%. • “Built-in Stereo” • Use one row axial-one row stereo • Can number of independent hits be reduced? Can space point replace 2 independent hits? • “More than Stereo” • Could try to use more than 2 views to rule out ambiguities and extract intrinsic “pixel” resolution • For example, use 4 views and double pitch (149 vs 74.5 mm) • Potential for much higher resolution in Z with no ghost hits • Is this useful for tracking?

  3. Designs with Separate ASIC and new FE • Either analogue and digital encoding • How short would “z” units have to be in order to maintain resolution in end cap?

  4. Embedded strip ASIC designs • Might be able to embed all/part of strip-like ASIC into CMOS sensor. If can get up to L1/R3 memory blocks into sensor would significantly reduce wire bonding • How to balance risk vs. production time and non-core costs? • Assuming this would be lower yield, would put even stronger priority on question is stitching really necessary.

  5. Pixel electronics • May be possible to go more pixel-like (FEI4 ASICs) • How big can pixels be and still be useful? • How is ROI trigger utilized in pixels?

  6. End cap “primer” • 20 segments in R in 6 rings (8, 4, 2, 2, 2, 2) • Lengths (mm): 8, 14, 14, 12, 12, 13 ,13 18, 24, 18, 21, 21, 31, 31, 58, 58, 54, 54, 49, 49 • Max Occupancies (%): 0.45, 0.74, 0.63, 0.53, 0.54, 0.54, 0.5, 0.66, 0.75, 0.54, 0.59, 0.7 0.64, 0.98, 0.89, 0.7,0.63,0.48, 0.46

  7. Endcap in CMOS • What would occupancy be like if made up of reticlelength strips? • Assume 24 mm strips everywhere with 74.5 mm pitch • Estimate the occupancy per mm in LOI end cap • Results in 24 segments (instead of 20) as strips shorter on average • Occupancy is 1.3%, 1.1%, 0.9%, 0.8%, 0.7%, 0.7%, 0.6%, 0.5%, 0.5%, 0.4%, 0.4%, 0.4%, 0.4%, 0.4%, 0.3%, 0.3%, 0.3%, 0.3%, 0.3%, 0.2%, 0.2%, 0.2%, 0.2%

  8. LOI occupancies

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