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Moving Verilog-AMS from Accellera to IEEE

Moving Verilog-AMS from Accellera to IEEE. Srikanth Chandrasekaran Technical Chair, Verilog-AMS Committee. Verilog-AMS Standards Committee – Scope & Purpose. The Verilog-AMS Standards committee aims to address the needs of the mixed signal design community

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Moving Verilog-AMS from Accellera to IEEE

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  1. Moving Verilog-AMS from Accellera to IEEE Srikanth Chandrasekaran Technical Chair, Verilog-AMS Committee

  2. Verilog-AMS Standards Committee – Scope & Purpose • The Verilog-AMS Standards committee aims to address the needs of the mixed signal design community • Enables top-down design methodology of AMS designs and allows designers to write early behavioral code of the mixed signal systems • Provides capabilities and features to enable system level design and verification • Standards committee comprises of team of experts in the AMS industry • Volunteers comprise of both the developers (EDA tool developers) as well as consumers (design community) • The Verilog-AMS committee has representation from about 10 companies that are either developing tools or mixed signal designs. • Ensuring Interoperability • Ensures any capability or enhancement done in the analog or the mixed signal part of the AMS language works with existing standards • Interoperability is key: Ease of understanding; uniform implementation of the particular implementation, developing portable design

  3. Beyond LRM2.3 • Alignment with System Verilog (SV-AMS Integration Efforts) • Having the unified BNF for Verilog-AMS with Verilog 1364-2005 as a subset means we are automatically aligned with System Verilog • Will allow the committee to take the next step and merge the analog and mixed signal constructs with the System Verilog language. • Plans to integrate Verilog-AMS with SV as part of IEEE p1800 dot standard • Subcommittee to look at outstanding enhancements and capabilities for mixed signal constructs • This effort will specifically look at the mixed signal items that have not been resolved in LRM2.3 and will be driven by Marq Kole from NXP • This activity will be in parallel to SV-AMS merger and is kept disconnected in terms of release for enabling maintenance and improvement of language from merger activities • Extending SV assertions to AMS • Need to extend the current SV assertions to the mixed signal language as part of the SV-AMS integration work

  4. Status & Moving Forward • Current Status: • LRM v2.3 released August 2008 through the Accellera Organization • The main focus of LRM v2.3 was integration with P1364-2005 IEEE standard • Moving Forward: • Plan to move the Verilog-AMS v2.3 as part of P1800 dot standard. The plan is to have it as a “corporate standard” within the IEEE organization • The SV-AMS committee will work on integrating the Verilog-AMS v2.3 with P1800-2009 IEEE standard. The next major version (internal name LRM v3.0) will be released as dot standard within P1800 • The committee will also oversee the efforts of driving the SVA extensions to Analog and the Mixed-signal behavior working groups • The Verilog-AMS v2.3 can be donated to the IEEE and can be used as the basis for the P1800 integration work • Open Questions: • The release of the SVA extensions to Analog and improvements to mixed signal behavior need to be de-linked from merger activities • Is it possible to release work from the sub-committees under Accellera Organization (LRM 2.4, etc). • This is very likely and needs to be enabled since SV-AMS merger might be bigger effort than the sub-committee efforts

  5. Verilog-AMS Committee Representatives • The Verilog-AMS committee has very broad and strong representation from various groups involved in AMS designs and tools • Representation from design organizations • Freescale Semiconductor Inc. • Analog Devices Inc. • NXP Semiconductors • Intel Corporation • True Circuits Corporation • Qualcomm Inc. • EDA vendor representation • Cadence Design Systems Inc. • Tiburon Design Automation Inc. • Mentor Graphics Corporation • Synopsys Inc. • Agilent • University & Consultants • University of Waterloo • ASTC Pty Ltd • Designer’s Guide Consulting

  6. Participating Members & Leadership • The expectation is that the participating membership will not essentially change once Verilog-AMS is moved under IEEE • Need to allow non-IEEE members to participate and contribute to the development of the LRM • Voting eligibility would be governed by the IEEE voting rules as defined for a “Corporate Standard” • The leadership for the SV-AMS P1800 dot standard working group will also remain the same • Sri Chandra (Freescale) will continue to be the technical chairperson of this working group driving the merger with SV • Individual leaders have been identified for the mixed signal behavioral extensions (Marq Kole, NXP is driving that effort) and SVA extensions to Analog (Anand Himyanshu from Freescale)

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