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Introduction to Verilog

Introduction to Verilog. Multiplexers. Introduction to Verilog. Verilog Hardware Description Language (Verilog HDL) released by Gateway Design Automation in 1983 Cadence buys Gateway in 1989 Cadence releases Verilog HDL to the public domain in 1990

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Introduction to Verilog

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  1. Introduction to Verilog Multiplexers

  2. Introduction to Verilog • Verilog Hardware Description Language (Verilog HDL) released by Gateway Design Automation in 1983 • Cadence buys Gateway in 1989 • Cadence releases Verilog HDL to the public domain in 1990 • Verilog adopted by the IEEE as IEEE standard 1364 in 1995

  3. Combinational Circuit Example n-line 2-to-1 Multiplexer n-line 2 x 1 MUX a(n-1:0) y(n-1:0) b(n-1:0) sel y 0 a 1 b sel

  4. a(n-1:0) n-line 2 x 1 y(n-1:0) MUX b(n-1:0) sel An n-line 2 x 1 MUX module mux2p(a,b,sel,y); parameter width = 2; input [width-1:0] a; input [width-1:0] b; input sel; output [width-1:0] y; reg [width-1:0] y; always @(sel, a, b) begin if(sel == 0) y = a; else y = b; end endmodule parameter statement defines width of bus

  5. An n-line 2 x 1 MUX module name module mux2p(a,b,sel,y); parameter width = 2; input [width-1:0] a; input [width-1:0] b; input sel; output [width-1:0] y; reg [width-1:0] y; always @(sel, a, b) begin if(sel == 0) y = a; else y = b; end endmodule reg defines y as a variable always sensitivity list Sequential statements (if…else) must be in an always block Note optional begin…end in always block

  6. An n-line 2 x 1 MUX module mux2p(a,b,sel,y); parameter width = 2; input [width-1:0] a; input [width-1:0] b; input sel; output [width-1:0] y; reg [width-1:0] y; always @(sel, a, b) begin if(sel == 0) y = a; else y = b; end endmodule Note: == is logical equality operator Note: = is a blocking assignment

  7. Digilab2 – DIO1 Boards Pushbutton bn Spartan II FPGA Four 7-segment displays 8 LEDs LD 8 Switches SW 4 Pushbuttons BTN 74HC373 latch ldg <= ‘1’

  8. Top-level Design – Lab 1

  9. module Lab1v(SW,BTN4,ldg,LD); input [1:8] SW; input BTN4; output ldg; output [1:4] LD; mux2p SWmux(.a(SW[1:4]),.b(SW[5:8]),.sel(BTN4),.y(LD)); defparam SWmux.width = 4; assign ldg = 1; // enable 74HC373 latch endmodule

  10. module Lab1v(SW,BTN4,ldg,LD); input [1:8] SW; input BTN4; output ldg; output [1:4] LD; mux2p SWmux(.a(SW[1:4]),.b(SW[5:8]),.sel(BTN4),.y(LD)); defparam SWmux.width = 4; assign ldg = 1; // enable 74HC373 latch endmodule

  11. module Lab1v(SW,BTN4,ldg,LD); input [1:8] SW; input BTN4; output ldg; output [1:4] LD; mux2p SWmux(.a(SW[1:4]),.b(SW[5:8]),.sel(BTN4),.y(LD)); defparam SWmux.width = 4; assign ldg = 1; // enable 74HC373 latch endmodule Note: defparamstatement used to override parameter width Note: assign statement used for concurrent logic equations

  12. Sel y “00” a “01” b “10” c “11” d An n-line 4 x 1 multiplexer a(n-1:0) n-line b(n-1 :0) 4 x 1 y(n-1 :0) c(n-1 :0) MUX d(n-1 :0) sel(1:0)

  13. sel y “00” a “01” b “10” c “11” d An n-line 4 x 1 multiplexer module mux4p(a,b,c,d,sel,y); parameter width = 4; input [width-1:0] a,b,c,d; input [1:0] sel; output [width-1:0] y; reg [width-1:0] y; always @(sel, a, b, c, d) case(sel) 0: y = a; 1: y = b; 2: y = c; 3: y = d; default: y = a; endcase endmodule Note: default is decimal Must include ALL posibilities in case statement Signals can have values 0, 1, z, x

  14. Top-level design module Lab1bv(SW,BTN,ldg,LD); input [1:8] SW; input [1:2] BTN; output ldg; output [1:2] LD; mux4p SWmux(.a(SW[1:2]),.b(SW[3:4]), .c(SW[5:6]),.d(SW[7:8]),.sel(BTN),.y(LD)); defparam SWmux.width = 2; assign ldg = 1; // enable 74HC373 latch endmodule

  15. Verilog Always Block always @(<sensitivity list>) begin <sequential statements> end Within an always block: Variables (reg) are assigned using = (Blocking) and are updated immediately. (Used for combinational signals) Sequential signals are assigned using <= (Non-blocking) and are updated at the end of the always block.

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