Introduction to Verilog

Introduction to Verilog GWU – ECE 2140 Spring 2012 Revised by Scott Trocchia

Contents of this mini-lecture • What are FPGAs? What’s inside them? • Brief Verilog History • What is Verilog? • Levels of Verilog Coding • Modules • Lots of Operators • Verilog Modeling • Always blocks • Continuous assignments

What are FPGAs? • FPGA = Field-Programmable Gate Array • Include space for lots of logic gates • Can be programmed… • …and reprogrammed ~100,000 times • Benefits include: • Cheap • Easy to program (barring errors) • Short amount of time for commercialization • etc.

Q: What’s inside an FPGA? A: This Let’s go back to 1984…

Brief Verilog History • A world without Verilog… • … was boring • In 1984, the language was created by Gateway Design Automation, Inc.

What is Verilog? • Hardware Description Language • Not meant to be understood for your operating system (Windows, Mac, Linux) • Used to describe digital systems, such as • Register (memory) • CPU • Network switch • Built-in functions: not, and, nand, nor, or, xor, xnor, buf, …

Levels of Verilog Coding • Behavioral level • A functional representation • How does my circuit work? • Register-Transfer Level (RTL) • How is data transferred from inputs to outputs? • Gate Level • What gates are contained within my circuit?

You’ve seen these before… modulehalf_adder(x, y, sum, carry); input x; input y; output sum; output carry; assign sum = x ^ y; assign carry = x & y; endmodule modulehalf_adder(A, B, Sum, C_out); input A; input B; output Sum; outputC_out; xor(Sum, A, B); and(C_out, A, B); endmodule

Module basics moduleMultiplexer(In,Select,Out); input[3:0]In; input[1:0]Select; outputregOut; always@(*)begin case(Select) 2'b00:Out<=In[0]; 2'b01:Out<=In[1]; 2'b10:Out<=In[2]; 2'b11:Out<=In[3]; endcase end endmodule Verilog is case-sensitive, so be mindful!

Data Types • reg – register – stores a value • wire – used for connecting logic • Number representation • Typical format is: (#bits)’(RADIX)(number) • RADIX: b=binary, h=hex, d=decimal • Example: 4’b1110 = 4’hE = 4’d14 • Negative numbers in 2’s complement

Verilog Operators • Arithmetic • Logical • Relational • Equality • Reduction • Shift • Concatenation • Conditional

Arithmetic Operators

More operators • Relational operators • Same as C • a < b, a > b, a <= b, a >= b • 1-bit result: 0 if false, 1 if true • Equality operators • a == b • a != b • Compared bit-by-bit • 1-bit result: 0 (false), 1 (true)

…More operators • Logical operators • Bit-wise operators

…Operators (cont’d.) • Shift • Left shift << • Right shift >> • Concatenation • {2’b10,2’b01}equals4’b1001 • regA,B,C;A=1'b0;B=2'b11;C={B,A};C= {A,B}; Will these operations give different results?

Operators (last one!) • Conditional Operators • Conditional_expression ? True_expr : false expr • Example: • x = 0; q = 0 • (if x < 0) ? (q = 0) : (q = 1);

Verilog modeling Part 2

Always Blocks • Executes loop over and over • Can only assign to registers in always blocks • 2 types • Level triggered - latch • Edge triggered – flip-flop always@(posedgeClk)begin if(Reset)begin data<=0; end elsebegin data<=q_in; end end

Always Blocks (Combinational) • Always blocks can be used for combinational logic too always@(*)begin case(Select) 2'b00:out<=A; 2'b01:out<=B; 2'b10:out<=C; 2'b11:out<=D; endcase end

Always Blocks (Sequential) • Sequential assignment inside block • Remember, this is HARDWARE • Example: • assume A=B=0 before always block executes always@(posedgeClk)begin A<=1; B<=A; end • What will B equal after always block execution?

Continuous Assignment • Can only be assigned to wires assignA=B^Y; assignC=Sel?TrueVal:FalseVal;

Questions • ? ? ?

References • http://en.wikipedia.org/wiki/Field-programmable_gate_array • http://www.asic-world.com/verilog/intro1.html#Introduction • http://en.wikipedia.org/wiki/Verilog • “Verilog – Representation of Number Literals”, http://web.engr.oregonstate.edu/~traylor/ece474/lecture_verilog/beamer/verilog_number_literals.pdf

Introduction to Verilog